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Details, datasheet, quote on part number:XR16C2852
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| Part: | XR16C2852 |
| Category: | Communication => UARTs |
| Description: | Dual Uart With TX And RX Fifo Counters, 128 Bytes of Fifos And Automatic RS-485 Half Duplex Control |
| Company: | Exar Corporation |
| Datasheet: | Download XR16C2852 datasheet File size : 362 kB |
| Request For quote: | Find where to buy XR16C2852
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Datasheet text preview:
XR16C2852
DUAL UART WITH 128-byte FIFOs AND RS-485 HALF DUPLEX DIRECTION CONTROL
July 1999
DESCRIPTION
The XR16C2852*1 (2852) is a dual universal asynchronous receiver and transmitter (UART). The device is designed for high performance communication systems to provide maximum full-duplex data throughput. Each UART provides enhanced functions with 128 byte of transmit and receive FIFOs, automatic RTS/CTS and software flow control, programmable FIFO trigger level, automatic RS-485 half duplex transmit/receive direction control, wireless infrared (IrDA ver 1.0) data encoder/decoder, and a modem control interface. Onboard status registers provide the user with error indications and operational status. An alternate function register supports concurrent write to UART A and B. System interrupts and modem control features may be tailored by software to meet user requirements. Independent programmable baud rate generators are provided to select data rates up to 1.5 Mbps. An internal loopback capability allows onboard diagnostics. The 2852 is available in a 44-pin PLCC package and is pin-to-pin and functionally compatible with the ST16C2552. The device is fabricated in advanced CMOS process to achieve low power and high speed requirements.
FEATURES
· Pin and functionally compatible to ST16C2552, and National PC16552/NS16C552 · Independent channel A/B control · Up to 1.5 Mbps data rate operation · 128 byte transmit FIFO to reduce CPU bandwidth requirement · 128 byte receive FIFO with error flags to reduce CPU bandwdth requirement · Programmable transmit and receive FIFO trigger level from 0 to 127 · Automatic RTS/CTS flow control with hysteresis · Automatic software flow control · Automatic RS485 half duplex direction control on -RTS pin. · Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line break) · Infrared (IrDA ver 1.0) transmit and receive data encoder/decoder · Device identification and revision · Standard 460.8 Kbps transmit/receive data rate with 7.3728 MHz crystal or external clock source · +5V or 3.3V operation · Industrial and commercial temperature grades · 44-pin PLCC package
PLCC Package
-TXRDYA -DSRA 41
44
43
42
D5 D6 D7 A0 XTAL1 GND XTAL2 A1 A2 CHSEL INTB
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
40
6
5
4
3
2
1
-CTSA
-CDA
VCC
-RIA
D4
D3
D2
D1
D0
39 38 37 36 35
RXA TXA -DTRA -RTSA -MFA INTA VCC -TXRDYB -RIB -CDB -DSRB
XR16C2852CJ
34 33 32 31 30 29
-MFB
RESET
-IOR
-RTSB
RXB
TXB
ORDERING INFORMATION
Part number Pins Package Operating temperature
XR16C2852CJ XR16C2852IJ
44 44
PLCC PLCC
0° C to + 70° C -40° C to + 85° C
Note*1: Covered by U.S. patent #5,649,122 and patent pending.
Rev. 1.00
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EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 · (510) 668-7000 · FAX (510) 668-7017
-DTRB
-CTSB
-CS
-IOW
GND
XR16C2852
D0-D7 -IOR -IOW RESET
Data bus & Control Logic
Transmit FIFO Registers
Transmit Shift Register
TX A/B TXIR A/B
Flow Control Logic Receive FIFO Registers
Ir Encoder
Register Select Logic
Inter Connect Bus Lines & Control signals
A0-A2 -CS CHSEL
Receive Shift Register
RX A/B RXIR A/B
Flow Control Logic
Ir Decoder
INT A/B -RXRDY A/B -TXRDY A/B
Interrupt Control Logic
Clock & Baud Rate Generator
XTAL1
Modem Control Logic
-DTR A/B -RTS A/B -MF A/B -CTS A/B -RI A/B -CD A/B -DSR A/B
XTAL2
Figure 2, Block Diagram
Rev. 1.00
2
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XR16C2852
SYMBOL DESCRIPTION
Symbol Pin 44 10 14 15 16 Signal type I I I I Pin Description
A0 A1 A2 CHSEL
Address-0 Select Bit. - Internal register address selection. Address-1 Select Bit. - Internal register address selection. Address-2 Select Bit. - Internal register address selection. Channel Select - UART channel A or B is selected by the logical state of this pin when the -CS is a logic 0. A logic 0 on CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Chip Select (active low) - This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2852. Bit-0 of the Alternate Function Register (AFR) can temporary override CHSEL function, allowing the user to write to both channel registers simultaneously with one write cycle. It is specially useful in the initialization routine. Data Bus (Bi-directional, tri-state) - These pins are the eight bit, three state data bus for transferring information to or from the controlling external CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Signal and power ground. Interrupt A-B (active high) - This function is associated with individual channel interrupts, INT A-B. Interrupts are enabled in the interrupt enable register (IER), and becomes a logic 1 whenever an interrupt condition exists. Interrupt conditions include: receive data buffer ready, receive data time-out, receive errors, transmit buffer empty, or when a modem status change is detected. Read strobe (active low ) - A logic 0 transition on this pin will load the contents of an Internal register defined by address bits A0-A2 onto the data bus (D0-D7) for access by user CPU. Write strobe (active low) - A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2. Multi-Function A-B - This function is associated with an individual channel function, A or B. User programmable bits 1-2 of the Alternate Function
-CS
18
I
D0-D7
2-9
I/O
GND INT A-B
12,22 34,17
Pwr O
-IOR
24
I
-IOW
20
I
-MF A-B
35,19
O
Rev. 1.00
3
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