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Details, datasheet, quote on part number:XR16C850
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Datasheet text preview:
XR16C850
UART with 128-byte FIFO's FIFO Counters and Half-duplex Control
June 1999-1
GENERAL DESCRIPTION
The XR16C850*1 (850) is a universal asynchronous receiver and transmitter (UART) and is pin compatible with the ST16C550,ST16C650A, and TI's TL16C750 UART. The 850 is an enhanced UART with 128 byte FIFOs, automatic hardware/software flow control, and data rates up to 1.5Mbps. It includes transmit/receive FIFO counters to increase data loading and unloading throughput. Onboard status registers provide error indications and operational status. Modem interface control is included and can be optionally configured to operate with the Infrared (IrDA) encoder/decoder. Internal loopback allows onboard diagnostics. The 850 is available in 40-pin PDIP, 44-pin PLCC, 48-pin TQFP, and 52-pin QFP packages. The 44, 48, and 52 pin versions provide both the standard (STD) mode or PC mode. The STD mode is compatible with the ST16C450, ST16C550, ST16C650A and TL16C750 while the PC mode supports standard PC COM port connections. The 40 PDIP pin package does not offer the PC mode.
D4 D3
PLCC Package
-DSR 41 -CTS 40 39 38 37 36 35 VCC N.C. -CD 42 -RI 43 D2 D1 D0
D5 D6 D7 RCLK RX N.C. TX CS0 CS1 -CS2 -BAUDOUT
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
44
6
5
4
3
2
1
RESET -OP1 -DTR -RTS -OP2 N.C. INT -RXRDY A0 A1 A2
XR16C850CJ "STD" MODE CONNE CTION
34 33 32 31 30 29
IOW
GND
IOR
-DDIS
-DSR 41
-TXRDY
XTAL1
XTAL2
-IOW
-IOR
N.C.
44
43
42
ˇ Pin to pin compatible to ST16C550, ST16C650A and TL16C750 ˇ Transmit/receive FIFO counters ˇ 128 bytes of Transmit/Receive FIFO ˇ RS-485 half duplex direction control ˇ Automatic software/hardware flow control ˇ Programmable, selectable transmit/receive trigger levels ˇ Infrared transmitter and receiver encoder/decoder ˇ Up to 1.5Mbps data rate ˇ Sleep mode (100ľA standby) ˇ Small 7x7mm TQFP ˇ +5 or 3.3 Volts operation ˇ Windows2 drivers available
40 39 38 37 36
FEATURES
D5 D6 D7 S2 RX A4 TX A5 A6 A7 -LPT1 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
-CTS
VCC
-CD
-RI
D4
D3
D2
D1
D0
A9
-AS
RE SE T -OP1 -DTR -RTS S3 GND IRQA IRQB A0 A1 A2
XR16C850CJ "PC" MODE CONNECTION
35 34 33 32 31 30 29
18
19
20
21
22
23
24
25
26
27 IRQC
-IOW
XTAL1
XTAL2
-IOR
A8
S1
A3
ORDERING INFORMATION
Part Number Pins P a c k a g e O p e r a t i n g Temperature Part Number Pins P a c k a g e O p e r a t i n g Temperature
XR16C850CP XR16C850CJ XR16C850CM XR16C850CQ
40 44 48 52
PDIP PLCC TQFP QFP
0° C to + 70° C 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C
XR16C850IP XR16C850IJ XR16C850IM XR16C850IQ
40 44 48 52
PDIP PLCC TQFP QFP
-40° C to + 85° C -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C
Note *1: Covered by U.S. patent # 5,649,122 and patent pending. Note *2: Windows is a trademark of Microsoft Corporation.
Rev. 1.20
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 ˇ (510) 668-7000 ˇ FAX (510) 668-7017
-LPT2
-AEN
GND
28
XR16C850
-DSR -C T S 38 VCC D10 -C D -R I D4 D3 D2 D1 D0 48 47 46 45 44 43 42 41 40 39 37 A9
D11 D5 D6 D7 S2 / RCLK A4 RX TX A5 / CS0 A6 / CS1 A7 / -CS2 -LP T1 / -BAUDOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32
SEL RESET -OP1/RS485 -DTR -RTS -OP2 / S3 INT / IRQA -RXRDY / IRQB A0 A1 A2
XR16C850CM
31 30 29 28 27 26 25
D0 D1 D2 D3 D4 D5
1 2 3 4 5 6 7
40 39 38 37 36 35 34
VCC -RI -CD -DSR -CTS RESET -OP1 -DTR -RTS -OP2 INT -RXRDY A0 A1 A2 -AS -TXRDY -DDIS IOR -IOR
BUS 8/16
D6 D7 RCLK RX TX CS0 CS1
-DACK -DSR -CTS VCC D10 -CD -RI D4 D3 D2 D1 D0 A9
9 10 11 12 13 14 15 16 17 18 19 20
XR16C850CP
8
33 32 31 30 29 28 27 26 25 24 23 22 21
CLKSE L
A3 / IOR
GN D
D12/- LPT2 / -DDIS
IRQC / -TXRDY
-AE N / -AS
A8 / IOW
XTAL1
XTAL2
-IOW
-IOR
S1
-CS2 -BAUDOUT
52
51
50
49
48
47
46
45
44
43
42
41
40
XTAL1
D11 D5 D6 D7 S 2 / RCLK A4 RX TX A 5 / CS0 A 6 / CS1 A 7 / -CS2 - L P T 1 / -BAUDOUT TC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 SEL RESET -OP1/RS485 -DTR -RTS - O P 2 / S3 I N T / IRQA - R X R D Y * / IRQB/DRQ A0 A1 A2 B U S 8/16 C L K 8/16
XTAL2 -IOW IOW GND
XR16C850CQ
33 32 31 30 29 28 27
D12/-LPT2 /- DDIS
CLKSEL
XTAL1
XTAL2
-IOW
A8 / IOW
GND
-DMA
-IOR
Figure 1. PACKAGE DESCRIPTION, 16C850
Rev. 1.20
2
IRQC / -TXRDY
-AEN /- AS
A3 / IOR
S1
XR16C850
D0-D7 -IOR,IOR -IOW,IOW RESET
Data bus & Control Logic
Transmit FIFO Registers
Transmit Shift Register
TX
Flow Control Logic Receive FIFO Registers
Ir Encoder
Inter Connect Bus Lines & Control signals
A0-A2 -AS CS0,CS1 -CS2 -DDIS
Register Select Logic
Receive Shift Register
RX
INT -RXRDY -TXRDY
Interrupt Control Logic
Flow Control Logic
Ir Decoder
Clock & Baud Rate Generator
XTAL1 RCLK XTAL2 -BAUDOUT
Modem Control Logic
-DTR,-RTS -OP1/RS485 -OP2 -CTS -RI -CD -DSR
Figure 2. BLOCK DIAGRAM (STANDARD MODE)
Rev. 1.20
3
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