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Details, datasheet, quote on part number:XR16C854/XR16C854D
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Datasheet text preview:
Preliminary Information
QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854
DESCRIPTION
The XR16C854 *1 (854) is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654. The 854 is an enhanced UART with 128 byte FIFOs, Independent Transmit and Receive FIFO counter, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The 854 is available in 64 pin TQFP, 68 pin PLCC, and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy integration with Motorola, and other popular microprocessors. The XR16C854CV (64 pin) offers three state interrupt control while the XR16C854DV provides constant active interrupt outputs. The 64 pin devices do not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a musical instrument clock input (MIDICLK). The 854 combines the package interface modes of the 16C554/654 and 68C554/654 series on a single integrated chip.
FEATURES
ˇ Compatibility with the Industry Standard ST16C554/654, ST68C554/654, TL16C554 ˇ 1.5 Mbps transmit/receive operation (24MHz) ˇ 128 byte transmit and receive FIFO ˇ Independent transmit and receive FIFO counter ˇ Automatic software/hardware flow control ˇ Programmable Xon/Xoff characters ˇ Software selectable Baud Rate Generator prescaleable clock rates of 1X, 4X. ˇ Four selectable, and Programmable Transmit/ Receive FIFO interrupt trigger levels ˇ Standard modem interface or infrared IrDA encoder/decoder interface ˇ Software flow control turned off optionally by any (Xon) RX character ˇ Independent MIDI interface on 100 pin packages ˇ 100 pin packages offer internal register FIFO monitoring and separate IrDA TX outputs ˇ Sleep mode ( 200ľA stand-by)
PLCC Package
INTSEL -CDD 63 60 59 58 57 56 55 54 -CDA GND VCC RXD 63 RXA -RID 62 -RIA D7 D6 D5 D4 D3 D2 D1 67 D0 66
68
65
-DSRA -CTSA -DTRA VCC -RTSA INTA -CSA TXA -IOW TXB -CSB INTB -RTSB GND -DTRB -CTSB -DSRB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
64
9
8
7
6
5
4
3
2
1
-DSRD -CTSD -DTRD GND -RTSD INTD -CSD TXD -IOR TXC -CSC INTC -RTSC VCC -DTRC -CTSC -DSRC
XR16C854CJ 16 MODE
53 52 51 50 49 48 47 46 45 44
-CDB
RXB
RXC
-RIC
-RXRDY
CLKSEL
-TXRDY
RESET
16/-68
XTAL1
XTAL2
ORDERING INFORMATION
Part number
XR16C854CJ XR16C854CV XR16C854DCV XR16C854CQ
68 64 64 100
Pins
PLCC TQFP TQFP QFP
Package Operating temperature
0° C to + 70° C 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C
Part number
XR16C854IJ XR16C854IV XR16C854DIV XR16C854IQ
Note *1: Patent Pending
68 64 64 100
Pins
PLCC TQFP TQFP QFP
Package Operating temperature
-40° C to + 85° C -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C
Rev. 1.00P EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 ˇ (510) 668-7000 ˇ FAX (510) 668-7017
-CDC
A2
A1
A0
GND
-RIB
-DTRB -DTRA INTB INTA -RTSB -RTSA -CTSA -CSB -CSA -IOW -TXB VCC TXA GND 9 8 7 6 5 4 3 2 1 15 -CDA -RIA RXA GND D7 D6 D5 D4 D3 D2 D1 D0 52 51 50 49 VCC RXD -RID -CDD 46 47 48 14 13 12 11 10
-DSRA
-CTSB 16
-DSRB 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 53 54 55 56 57 58 59 60 61 62 63 -CDB -RIB RXB VCC A2 A1 A0 XTAL1
80 79 78 77 76 -CSRDY N.C. N.C. N.C. N.C.
-CDA
-RIA
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
-RID
-CDD
-RXRDYD
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
-TXRDYD
XR16C854
N.C.
1
100 -RXRDYA
Figure 1, Package Descriptions
Rev. 1.00P
64
XR16C854CV
N.C.
2
XTAL2 RESET GND RXC -RIC -CDC -DSRC
XR16C854DCV
N.C.
3
N.C.
4
-TXRDYA 75 74 73 72 71 70 -RTSD GND -DTRD -CTSD -DSRD IRTXD
5
64 Pin TQFP Package
IRTXA
6
-DSRA
7
-CTSA
8
-DTRA
9
VCC
10
-RTSA
11
TXC
TXD
VCC
-IOR
GND
INTC
INTD
-CSC
-CSD
INTA 69 68 67 66 65 TXC -IOR TXD -CSD INTD
12
-CTSC
-RTSC
-RTSD
-CTSD
-DTRC
-DTRD
-DSRD
-CSA
13
TXA
14
XR16C854CQ
100 Pin QFP Package
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A2
A1
A0
-RIB
RXB
-CDB
GND
RXC
-RIC
16/-68
XTAL1
XTAL2
RESET
-CDC
CLKSEL
-RXRDYB
MIDICLK
-RXRDY
-TXRDY
-RXRDYC
2
GND -DTRB -CTSB -RTSB R/-W
64 -CSC
-IOW
15
TXB
16
-DSRA
-RTSA
-CTSA
-DTRA
-CSB
17
-IRQ
VCC
N.C. A3
-CS
TXB
TXA
INTB 63 INTC
18
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
-RTSB 62 61 VCC -RTSC
19
GND
20
-DTRB 60 59 58 57 56 -TXRDYC IRTXC -DSRC -CTSC -DTRC
21
-CDB -RIB RXB CLKSEL 16/-68 A2 A1 A0 XTAL1 XTAL2 -RESET -RXRDY -TXRDY GND RXC -RIC 32 33 34 35 36 37 38 39 40 41 42 31 30 29 28
27
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62
-CDA -RIA RXA GND D7 D6 D5 D4 D3 D2 D1 D0 N.C. VCC RXD -RID
-CTSB
22
-DSRB
23
IRTXB
24
-TXRDYB 55 54 53 52 51 N.C. N.C. N.C. N.C. N.C.
25
N.C.
26
N.C.
27
N.C.
28
N.C.
29
68 Pin PLCC Package
XR16C854CJ 68 MODE
N.C.
30
45 -CTSC
46 -DTRC
47 VCC
48 -RTSC
49 N.C.
50 A4
51 TXC
52 N.C.
53 TXD
54 N.C.
55 N.C.
56 -RTSD
57 GND
58 -DTRD
59 -CTSD
60 -DSRD
XR16C854
Figure 2, Block Diagram 16 Mode
D0-D7 -IOR -IOW RESET
Data bus & Control Logic
Transmit FIFO Registers
Transmit Shift Register
TX A-D
Flow Control Logic Inter Connect Bus Lines & Control signals Receive FIFO Registers
Ir Encoder Receive Shift Register
A0-A2 -CS A-D
Register Select Logic
RX A-D RXIR A-D
INT A-D -RXRDY A-D -TXRDY A-D INTSEL
Interrupt Control Logic
Flow Control Logic
Ir Decoder
-DTR A-D -RTS A-D Clock & Baud Rate Generator Modem Control Logic -CTS A-D -RI A-D -CD A-D -DSR A-D
XTAL1 MIDI XTAL2
Rev. 1.00P
3
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