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Details, datasheet, quote on part number:XR16C864
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Datasheet text preview:
XR16C864
QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO July 2000 DESCRIPTION
The XR16C8641 (864) is a universal asynchronous receiver and transmitter (UART) with a dual interface compatible with the ST16C554/654/854 and ST68C554. The 864 is an enhanced UART with 128 byte FIFO's, Independent Transmit and Receive FIFO counters, RS-485 Support, Independent Transmit and Receive DMA signals, automatic hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The 864 is available in 100 pin QFP packages. The XR16C864 offers faster channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs and a separate clock for channel C (CHCCLK) that can be used as a musical instrument clock input. The 864 combines the package interface modes of the 16C554/654 and 68C554/654 series on a single integrated chip.
FEATURES
ˇ Compatibility with the Industry Standard ST16C554/654, ST68C554/654, TL16C554 ˇ 1.5 Mbps transmit/receive operation (24MHz) ˇ 128 byte transmit FIFO ˇ 128 byte receive FIFO with error flags ˇ Automatic RS-485 half-duplex switch ˇ Independent transmit and receive DMA signals ˇ Independent transmit and receive FIFO counter ˇ Automatic software/hardware flow control ˇ Programmable Xon/Xoff characters ˇ Software selectable Baud Rate Generator prescaleable clock rates of 1X, 4X. ˇ Four selectable, and Programmable Transmit/ Receive FIFO interrupt trigger levels ˇ Standard modem interface or infrared IrDA encoder/decoder interface ˇ Software flow control turned off optionally by any (Xon) RX character ˇ Independent clock input for channel C ˇ FIFO monitoring and separate IrDA TX outputs ˇ Sleep mode ( 200ľA stand-by) ˇ 100-pin QFP packages
Figure 1, Pinout of the Device
-RXRDYD/DREQD 82 100 -RXRDYA/DRQA -TXRDYD/DREQD 81
INTSEL
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
BC LK A -O P 2 A R S 4 8 5 /-O P 1 A DACKA D R E Q A /-T X R D Y A IR T X A -D S R A -C T S A -D T R A VCC -R T S A IN T A -C S A TXA -IO W TXB -C S B IN T B -R T S B GND -D T R B -C T S B -D S R B IR T X B D R E Q B /-T X R D Y B DACKB AEN R S 4 8 5 /-O P 1 B -O P 2 B R C LKB
1 2 3 4 5 6 7 8 9 10 11
83
-CDD
-CDA
GND
VCC
RXD
RXA
-RID
-RIA
D7
D6
D5
D4
D3
D2
D1
D0
80 79 78 77 76 75 74 73 72 71 70
BC LK D -O P 2 D - O P 1 D /R S 4 8 5 DACKD -C S R D Y IR T X D -D S R D -C T S D -D T R D GND -R T S D IN T D -C S D TXD -IO R TXC -C S C IN T C -R T S C VCC -D T R C -C T S C -D S R C IR T X C -T X R D Y C /D R E Q C DACKC TC - O P 1 C /R S 4 8 5 -O P 2 C BC LK C
XR16C864CQ
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 -CDC
CLKSEL
RESET
-CDB
16/-68
GND
XTAL1
XTAL2
RXC
RXB
-RIB
A2
A1
A0
CHCCLK
-RIC
ORDERING INFORMATION
Part number Pins Package Operating temperature
XR16C864CQ XR16C864IQ
100 100
QFP QFP
0° C to + 70° C -40° C to + 85° C
Note 1: Covered by US Patent # 5,649,122
Rev. 1.10
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 ˇ (510) 668-7000 ˇ FAX (510) 668-7017
DREQC/-RXRDYC
DREQB/-RXRDYB
-RXRDY
-TXRDY
50
XR16C864
Figure 2, Block Diagram 16 Mode
D0-D7 -IOR -IOW RESET TC
Data bus & Control Logic
Transmit FIFO Registers
Transmit Shift Register
TX A-D
Flow Control Logic Receive FIFO Registers
Ir Encoder
Register Select Logic
Inter Connect Bus Lines & Control signals
A0-A2 -CS A-D AEN
Receive Shift Register
RX A-D RXIR A-D
INT A-D -RXRDY A-D -TXRDY A-D INTSEL DREQ A-D DACK A-D
Flow Control Logic
Ir Decoder
Interrupt Control Logic
Clock & Baud Rate Generator
XTAL1 MIDI XTAL2 BCLK A-D
Modem Control Logic
-DTR A-D -RTS A-D -OP1 A-D RS485 A-D -CTS A-D -RI A-D -CD A-D -DSR A-D
Rev. 1.10
2
XR16C864
Figure 3, Block Diagram 68 Mode
D 0 -D 7 R /-W -R E S E T
Data bus & Control Logic
T r a n s m it F IF O R e g iste rs
T r a n s m it S h ift R e g iste r
T X A -D
F lo w C o n tro l L o g ic Inter Connect Bus Lines & Control signals R e c e iv e F IF O R e g iste rs
Ir E n coder
Register Select Logic
A 0 -A 4 -C S AEN
R e c e iv e S h ift R e g iste r
R X A -D R X IR A -D
-R X R D Y -T X R D Y DREQ DACK
IR Q A -D A -D A -D A -D
Interrupt Control Logic
F lo w C o n tro l L o g ic
Ir D ecoder
Clock & Baud Rate Generator
XTAL1 CH CCLK XTAL2 B C L K A -D
M odem C o n tro l L o g ic
-D T R A -D -R T S A -D -O P 1 A -D R S 4 8 5 A -D -C T S A -D -R I A -D -C D A -D -D S R A -D
Rev. 1.10
3
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