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Details, datasheet, quote on part number:XR16L2450IM
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Datasheet text preview:
PRELIMINARY
JUNE 2003
XR16L2450
2.25V TO 5.5V DUART
REV. P1.0.2
GENERAL DESCRIPTION
The XR16L2450 (L2450) is a dual universal asynchronous receiver and transmitter (UART). The XR16L2450 is an improved version of the ST16C2450 with lower operating voltage and 5 volt tolerant inputs. The L2450 provides enhanced UART functions, a modem control interface and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications and operational status. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 1.5 Mbps. An internal loopback capability allows onboard diagnostics. The L2450 is available in a 44pin PLCC and 48-pin TQFP packages. The L2450 is fabricated in an advanced CMOS process capable of operating from 2.25 volt to 5.5 volt power supply with 5 volt tolerant inputs. APPLICA TIONS · Portable Appliances · Telecommunication Network Routers · Ethernet Network Routers · Cellular Data Devices · Factory Automation and Process Controls FIGURE 1. XR16L2450 BLOCK DIAGRAM
FEATURES · 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Pin-to-pin compatible to Exar's ST16C2450, ST16C2550, XR16L2550, XR16L2750 and X R 16C2850 · Pin-to-pin compatible to TI's TL16C752B on the 48TQFP package · 2 independent UART channels · Up to 1.5 Mbps data rate with a 24 MHz crystal oscillator or external clock frequency · 1 byte Transmit FIFO · 1 byte Receive FIFO with error tags · Status report registers · Modem control signals (CTS#, RTS#, DSR#, DTR#, RI#, CD#) · Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity · Crystal oscillator or external clock input · TTL compatible inputs, outputs · Industrial temperature ranges · 48-TQFP and 44-PLCC packages
A2 :A0 D 7 :D 0 IOR# IO W # C SA# C SB# I N TA I N TB 8-bit Data Bu s Interface
* 5 Volt Tolerant Inputs (Except External Clofck Input) UART Channel A U AR T Regs BR G 16 Byte TX FIFO T X & RX 16 Byte RX FIFO
2.25 to 5.5 Volt VCC G ND
T XA, RXA, DTRA#, DSRA#, RTSA#, DTS A#, CDA#, RIA#, O P2 A#
UART Channel B (same as Channel A)
T XB, RXB, DTRB#, DSRB#, RTSB#, CTS B#, CDB#, RIB#, O P2 B# XT AL 1 XT AL 2
Reset
Crystal Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538· (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
PRELIMINARY
FIGURE 2. PIN OUT ASSIGNMENT
D SR A#
VC C
R IA#
C TS A#
C DA #
48
NC
47
46
45
44
43
42
41
40
38
39
37
NC
D4
D3
D2
D1
D0
13
15
18
19
20
22
16
14
17
21
23
D SR B#
R T S B#
C T S B#
C DB #
GND
NC
XT AL1
XT AL2
IO W #
IO R #
R I B#
D S RA #
44
43
42
41
D5 D6 D7 RX B RX A
7 8 9 10 11
40
6
5
4
3
2
1
C TSA #
CDA #
R IA#
V CC
NC
D4
D3
D2
D1
D0
NC
24
XTAL 1 18
XTAL 2 19
IO W# 20
CDB# 21
GN D 22
NC 23
IO R# 24
D SRB# 25
R IB# 26
R TSB # 27
Dev ic e
ORDERING INFORMATION
PART NUMBER XR16L2450IJ XR16L2450IM PACKAGE 44-Lead PLCC 48-Lead TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active Active
2
C TSB # 28
rx rx rx rx
XR16L2450 2.25V TO 5.5V DUART
REV. P1.0.2
D5 D6 D7 R XB R XA NC TX A TX B O P2 B#
1 2 3 4 5 6 7 8 9
36 35 34 33
R ESE T D T R B# D T R A# R T S A# O P2 A# NC IN TA IN TB A0 A1 A2 NC
XR1 6L24 50 48 -p in TQFP
32 31 30 29 28 27 26 25
C SA# 10 C SB# 11 N C 12
39 38 37 36
RE S E T DT RB # DT RA # RT S A #
35 O P2A#
NC 12 T XA T XB 13 14
X R 16 L 24 50 4 4- pin PLCC
34 33 32 31
NC INTA INTB A0
O P2B# 15 CSA # 16 CSB # 17
30 A1 29 A2
XR16L2450 2.25V TO 5.5V DUART
REV. P1.0.2
PRELIMINARY
PIN DESCRIPTIONS
Pin Description
NAME 44-PLCC PI N # 48-TQFP PI N # TYPE DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 29 30 31 9 8 7 6 5 4 3 2 24 26 27 28 3 2 1 48 47 46 45 44 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional).
IO
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART channel A select (active low) to enable UART channel A in the device for data bus operation. UART channel B select (active low) to enable UART channel B in the device for data bus operation. UART channel A Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0 (Default). UART channel B Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0 (Default).
IOW#
20
15
I
CSA# CSB# INTA
16 17 33
10 11 30
I I O
INTB
32
29
O
MODEM OR SERIAL I/O INTERFACE TXA RXA 13 11 7 5 O I UART channel A Transmit Data. If it is not used, leave it unconnected. UART channel A Receive Data. Normal receive data input must idle at logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor. UART channel A Request-to-Send (active low) or general purpose output. If it is not used, leave it unconnected. UART channel A Clear-to-Send (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.
RTSA# CTSA#
36 40
33 38
O I
3
rx rx rx rx
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