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Details, datasheet, quote on part number:XR16L2550IM
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Datasheet text preview:
PRELIMINARY
JUNE 2003
XR16L2550
REV. P1.0.3
LOW VOLTAGE DUART WITH 16-BYTE FIFO
GENERAL DESCRIPTION
The XR16L25501 (L2550) is a dual universal asynchronous receiver and transmitter (UART). The XR16L2550 is an improved version of the ST16C2550 UART with lower operating voltages and 5 volt tolerant inputs. The L2550 provides enhanced UART functions with 16 byte FIFOs, a modem control interface and data rates up to 4 Mbps. Onboard status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by external software to meet specific user requirements. Independent programmable baud rate generators are provided to select transmit and receive clock rates up to 4 Mbps. The Baud Rate Generator can be configured for either crystal or external clock input. An internal loopback capability allows onboard diagnostics. The L2550 is available in a 44-pin PLCC, 48-pin TQFP and 32-pin QFN packages. The L2550 is fabricated in an advanced CMOS process.
NOTE:
1 Covered by U.S. Patent #5,649,122.
FEATURES
· 2.25 to 5.5 Volt operation · 5 Volt tolerant inputs · Pin-to-pin compatible to Exar's ST16C2450,
ST16C2550 and XR16L2750 in 44-PLCC and 48TQFP packages
· Pin-to-pin compatible to XR16C2850 in 44-PLCC · Pin alike XR16L2551, XR16L2751 and
XR16C2850 in 48-TQFP package
· Two independent UART channels
s s s
s
s
s s s s
APPLICATIONS
· Por table Appliances · Medical Monitors · Base Stations · Micro Servers · Telecommunication Network Routers · Industrial Automation Controls
FIGURE 1. XR16L2550 BLOCK DIAGRAM
s
Up to 4 Mbps with external clock of 64 MHz Register Set compatible to 16C550 16 byte Transmit FIFO to reduce the bandwidth requirement of the external CPU 16 byte Receive FIFO with error tags to reduce the bandwidth requirement of the external CPU 4 selectable Receive FIFO interrupt trigger levels Automatic RTS/CTS hardware flow control Automatic Xon/Xoff software flow control W ireless infrared encoder/decoder Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#) Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity
· Tiny 32-QFN, no lead package (5x5x0.9mm) · 44-PLCC and 48-TQFP packages also available
A 2 :A 0 D7:D0 IO R # IO W # CS A # CS B # IN T A IN T B T XR D Y A# T XR D Y B# R X R D YA # R D R X YB # Res et
* 5 Volt Tolerant Inputs ( E x c e p t External Clock Input)
2 .2 5 to 5.5 Volt VCC GND
U A R T Channel A UA RT Reg s 8 - b it Data B us In te r fa c e B RG 1 6 Byte TX FIFO T X & RX 1 6 Byte RX FIFO T X B , RXB, DTRB#, D S R B # , RTSB#, C T S B # , CDB#, RIB#, O P 2 B# X TA L 1 X TA L 2 T X A , RXA, DTRA#, D S R A # , RTSA#, D T S A # , CDA#, RIA#, O P 2 A#
U A R T Channel B ( s a m e as Channel A)
C r y s ta l Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538· (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
PRELIMINARY
FIGURE 2. PIN OUT ASSIGNMENT
TXRDYA# DSRA#
VCC
CTSA#
R IA #
CDA#
48
47
46
45
44
43
42
41
40
38
39
37
NC
D4
D3
D2
D1
D0
CSB# 1 1 NC 1 2 15 13 16 RXRDYB# 1 8 19 20 21 22 14 17 23 24
26 25
A2
D1
31 D4
D3
D5
30
29
D2
27
D0
NC
26
32
DSRB#
RTSB#
CTSB#
CDB#
X T A L2
X T A L1
IOW #
IOR#
R IB #
GND
NC
28
25
CTSA#
VCC
T X RD Y A #
D S RA #
C TSA #
CDA #
R IA#
V CC
D4
D3
D2
D1
D0
44
43
42
41
40
6
5
4
3
2
1
10 11
13
12
14
D5 D6 D7 RX B RX A
7 8 9 10 11
39 38 37 36
RE S E T
GND IOR # RTSB#
15
DT RB # DT RA # RT S A #
35 O P2A#
TXRDY B# 12 T XA T XB 13 14
X R 16 L 25 50 4 4- pin PLCC
34 33 32 31
RX R DY A # INTA INTB A0
O P2B# 15 CSA # 16 CSB # 17 XTAL 1 18 XTAL 2 19 IO W# 20 CDB# 21 GN D 22 R XRD YB# 23 IO R# 24 D SRB# 25 R IB# 26 R TSB # 27 C TSB # 28
30 A1 29 A2
ORDERING INFORMATION
PART NUMBER XR16L2550IL XR16L2550IJ XR16L2550IM PACKAGE 32-Lead QFN 44-Lead PLCC 48-Lead TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C DEVICE STATUS Active Active Active
2
CTSB#
XTAL1
XTAL2
IOW#
NC
16
9
D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP 2 B # 1 2 3 4 5 6 7 8 9 CSA# 1 0
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
REV. P1.0.3
36 35 34 33
RESET DT RB# DT RA# RTSA# OP 2 A # RXRDYA# INT A INT B A0 A1
X R 16 L2 5 50 4 8- pin TQFP
32 31 30 29 28 27
D6 D7 RXB RXA TXA TXB CSA# CSB#
1 2 3 4 5 6 7 8 XR16L2550 32-pin QFN
24 23 22 21 20 19 18 17
RESET RTSA# INTA INTB A0 A1 A2 NC
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
REV. P1.0.3
PRELIMINARY
PIN DESCRIPTIONS
Pin Description
NAME 32-QFN PI N # 44-PLCC PI N # 48-TQFP PI N # TYPE DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 18 19 20 2 1 32 31 30 29 28 27 14 29 30 31 9 8 7 6 5 4 3 2 24 26 27 28 3 2 1 48 47 46 45 44 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional).
IO
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART channel A select (active low) to enable UART channel A in the device for data bus operation. UART channel B select (active low) to enable UART channel B in the device for data bus operation. UART channel A Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode (active high) and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0 (Default). UART channel B Interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0 (Default).
IOW#
12
20
15
I
CSA# CSB# INTA
7 8 22
16 17 33
10 11 30
I I O
INTB
21
32
29
O
TXRDYA#
-
1
43
O
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. If it is not used, leave it unconnected.
3
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