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Details, datasheet, quote on part number:XR16L2551
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Datasheet text preview:
PRELIMINARY
JUNE 2003
XR16L2551
REV. P1.0.3
LOW VOLTAGE DUART WITH POWERSAVE
GENERAGENERAL DESCRIPTION
The XR16L2551 (L2551) is a low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device includes additional capability over the ST16C2550: Intel and Motorola data bus interface selection, hardware and software flow control, infrared encoder/ decoder, sleep mode and a PowerSave mode for batter y operation. The L2551's enhanced register set is compatible to the ST16C2550 and XR16L2550. It suppor ts the Exar's enhanced features of 16 bytes of TX and RX FIFOs and a complete modem interface. Onboard registers provide the user with operational status and data error tags. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generator is provided in each channel to support data rates up to 4 Mbps.
NOTE:
1 Covered by U.S. Patent #5,649,122.
FEATURES
· 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Intel or Motorola Bus Interface Select (16/68#)
pin
· Pin-to-pin compatible to XR16L2751CM · Two Independent UARTs
s
s
s s s s s s
APPLICATIONS
· Battery Operated Instruments · Data Port Adapters · Handheld Appliances · Radio Frequency Data Modems · Base Stations · USB Hubs · Industrial Automation Controls
FIGURE 1. XR16L2551 BLOCK DIAGRAM
s
Up to 4 Mbps at 5V, 3 Mbps at 3.3V, and 2 Mbps at 2.5V with external clock input Up to 1.5 Mbps at 5V, 1.25 Mbps at 3.3V and 1 Mbps at 2.5V with crystal clock input 16 bytes of Transmit and Receive FIFOs Automatic RTS/CTS hardware flow control Automatic Xon/Xoff software flow control W ireless infrared encoder/decoder Receive FIFO trigger levels select Programmable character lengths (5, 6, 7 or 8) with even, odd, forced or no parity Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#) in the 48-TQFP package
· Sleep Mode with PowerSave feature for battery
operation
· Industrial Temperature range · Tiny 32-QFN, no lead package (5x5x0.9mm) · 48-TQFP Package
PwrSave A2:A0 D7:D0 IOR# (VCC) IOW# (R/W#) CSA# (CS#) CSB# (A3) INTA (IRQ#) INTB (logic 0) TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset (Reset#) 16/68#
*5 Volt Tolerant Inputs (Except External Clock Input)
2.25 to 5.5 Volt VCC GND
UART Channel A UART Regs BRG 16 Byte TX FIFO TX & RX IR ENDEC TXA, RXA, RTSA#, CTSA#, ( DTR#, DSR# CD#, RIA#, OP2A# )
16 Byte RX FIFO TXB, RXB, RTSB#, CTSB#, ( DTRB#, DSRB# CDB#, RIB#, OP2B# ) XTAL1 XTAL2
Intel or Motorola Data Bus Interface
UART Channel B (same as Channel A)
Crystal Osc/Buffer
2551BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538· (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
PRELIMINARY
FIGURE 2. PIN OUT ASSIGNMENT
CTSA#
VCC
30
29
26
32
31
28
27
25
32
30
29
28
26
31
D6 D7 RXB RXA TX A TX B CSA# CSB#
1 2 3 4 5 6 7 8 11 13 12 14 10 15 16 9
24 23 22
RESET RTSA# I NTA I NTB A0 A1 A2 16/ 68# A3 (CSB#) 8 11 13 12 14 10 15 16 9 17 16/ 68# G ND VCC D6 D7 RXB RXA TX A TX B CS# 1 2 3 4 5 6 7 24 23 22 RESET# (Reset) RTSA# I RQ # NC (INTB) A0 A1 A2
XR16L2551 32-pi n QFN in 16 (Intel) Mode
21 20 19 18 17
XR16L2551 32-pi n QFN in 68 (Motorola) Mode
27
25
CTSA#
D4
D3
D2
D1
D5
D0
VCC
D4
D5
D3
D2
D1
D0
I OR#
RTSB#
PWRSAVE
CTSB#
XTAL2
XTAL1
I OW#
G ND
G ND
RTSB#
PWRSAVE
TXRDYA#
TXRDYA#
VCC (IOR#)
CTSB#
XTAL2
XTAL1
R/W#
DSRA#
DSRA#
VCC
VCC
CTSA#
CTSA#
RIA#
RIA#
CDA#
CDA#
48
47
46
45
44
43
42
41
40
48
40
38
D5 D6 D7 RXB RXA TXRDYB# TXA TXB
1 2 3 4 5 6 7 8
36 RESET 35 34 33 32 DTRB# DTRA# RTSA# OP2A# RXRDYA# INTA INTB A0 A1 A2 NC
39
39
37
47
46
45
44
43
42
41
38
37
NC
D4
NC
D3
D4
D3
D2
D1
D0
D2
D1
D0
15
13
16
18
19
15
19
20
21
22
14
17
23
13
16
18
20
21
22
23
CDB#
GND
RXRDYB#
RTSB#
RXRDYB#
VCC
DSRB#
DSRB#
CTSB#
RTSB#
CTSB#
XTAL1
XTAL1
16/68#
XTAL2
16/68#
XTAL2
CDB#
IOW#
IOW#
IOR#
RIB#
GND
RIB#
VCC
24
14
17
24
ORDERING INFORMATION
PAR T NUMBER XR16L2551IL XR16L2551IM PACKAGE 32-Lead QFN 48-Lead TQFP O PERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active Active
OP2B# 9 CSA# 10 CSB# 11 PWRSAVE 12
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
REV. P1.0.3
21 20 19 18
D5 D6 D7 RXB RXA TXRDYB# TXA TXB
1 2 3 4 5 6 7 8
36 RESET# 35 34 33 32 DTRB# DTRA# RTSA# OP2A# RXRDYA# IRQ# NC A0 A1 A2 NC
XR16L2551 48-pin TQFP in 16 (Intel) Mode
31 30 29 28 27 26 25
XR16L2551 48-pin TQFP in 68 (Motorola) Mode)
31 30 29 28 27 26 25
OP2B# 9 CS# 10 A3 11
PWRSAVE 12
GND
2
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
REV. P1.0.3
PRELIMINARY
PIN DESCRIPTIONS
Pin Description
NAME 32-QFN PIN # 48-TQ FP PIN # TYPE DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# ( VCC) 18 19 20 2 1 32 31 30 29 28 27 14 26 27 28 3 2 1 48 47 46 45 44 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.
IO
D ata bus lines [7:0] (bidirectional).
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used and should be connected to VCC. When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the Motorola bus interface. When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is at logic 0, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation.
IOW# (R/W#)
12
15
I
CSA# (CS#)
7
10
I
CSB# (A3)
8
11
I
INTA (IRQ#)
22
30
O
3
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