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Details, datasheet, quote on part number:XR16L2552
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Datasheet text preview:
PRELIMINARY
JUNE 2003
XR16L2552
REV. P1.0.3
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
GENERAL DESCRIPTION
The XR16L2552 (L2552) is a dual universal asynchronous receiver and transmitter (UART) with 5 volt tolerant inputs. The XR16L2552 is an improved version of the ST16C2552 UART with lower operating voltages and 5 volt tolerant inputs. The L2552 provides enhanced UART functions with 16 byte TX and RX FIFOs, automatic hardware (RTS/CTS) and software (Xon/Xoff) flow control, and a complete modem control interface. Onboard status registers provide the user with error indications and operational status. Indepedendent programmable baud rate generators are provided to select transmit and receive clock rates up to 4 Mbps. An internal loop-back capability allows onboard diagnostics. The L2552 provides block mode data transfers (DMA) through FIFO controls. DMA transfer monitoring is provided through the signals TXRDY# and RXRDY#. An Alternate Function Register provides the user with the ability to write the control registers for both UARTs concurrently and selection of the Multi-Function output (Baudout#, OP2#, or RXRDY#).
NOTE:
1 Covered by U.S. Patent #5,649,122.
FEATURES
· 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Pin-to-pin and functionally compatible to National
P C 16552
· Pin-to-pin Compatible to Exar's ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
· 2 Independent UART Channels
s s s
s
s s s s s
APPLICA TIONS
s
· Por table Appliances · Telecommunication Network Routers · Ethernet Network Routers · Cellular Data Devices · Factory Automation and Process Controls
FIGURE 1. XR16L2552 BLOCK DIAGRAM
s
Up to 4 Mbps with external clock of 64 MHz Register Set Compatible to 16C550 16 byte Transmit FIFO to reduce the bandwidth requirement of the external CPU 16 byte Receive FIFO with error tags to reduce the bandwidth requirement of the external CPU 4 selectable RX FIFO Trigger Levels Automatic RTS/CTS hardware flow control Automatic XonXoff software flow control W ireless infrared encoder/decoder Full Modem Interface (CTS#, RTS#, DSR#, DTR#, RI#, CD#) Programmable character lengths (5, 6, 7, 8) with even, odd, or no parity Multi-Function output allows more package functions with fewer I/O pins
· Concurrent write to Channels A and B · Crystal oscillator or external clock input · 48-TQFP (7x7x1.0 mm) and 44-PLCC packages
A2 :A0 D 7 :D 0 IOR# IO W # C S# C H SEL I N TA I N TB T XRDY# A/B RXRDY# A/B
(48-T QFP Only)
* 5 Volt Tolerant Inputs (Except External Clock Input) UART Channel A U AR T Regs BR G 8-bit Data Bu s Interface 16 Byte TX FIFO T X & RX 16 Byte RX FIFO
2.25 to 5.5 Volt VCC G ND
T XA
R XA T XB R XB
UART Channel B (same as Channel A)
MF A#
(OP 2A #, B AUDOUTA#, or RXRDY A#)
Crystal Osc/Buffer Modem Control Logic
MF B#
(OP 2B #, B AUDOUTB#, or RXRDY B#)
XT AL 1 XT AL 2 CTS #A /B, RI#A/B, CD#A/B, DSR#A/B DTR#A/B, RTS#A/B
2552BLK
Reset
Exar Corporation 48720 Kato Road, Fremont CA, 94538· (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
PRELIMINARY
FIGURE 2. PIN OUT ASSIGNMENTS
TXRDYA#
DSRA#
VCC
RIA#
CTSA#
CDA#
D2
D1
48
D0
47
46
45
44
43
42
41
40
38
39
37
NC
D4
D3
T X RD Y A #
15
13
16
18
19
20
21
22
14
17
23
24
DS RA #
RESET
RTSB#
DTRB#
CTSB#
MFB#
IOW#
IOR#
GND
44
43
42
41
D5 D6 D7 A0
7 8 9 10
40
6
5
4
3
2
1
CT S A #
CDA #
RI A #
RXB
TXB
V CC
CS#
NC
D4
D3
D2
D1
D0
CS# 18
M FB# 19
IO W# 20
RE SET 21
GN D 22
RTSB # 23
IO R# 24
RX B 25
TXB 26
DTR B# 27
ORDERING INFORMATION
PART NUMBER XR16L2552IM XR16L2552IJ PACKAGE 48-Lead TQFP 44-Lead PLCC OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active Active
2
CTSB # 28
rx rx rx rx
D5 D6 D7 A0 XTAL1 GND XTAL2 RXRDYB# A1 A2 CHSEL INTB 1 2 3 4 5 6 7 8 9 10 11 12
XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. P1.0.3
48-TQFP PACKAGE
36 35 34 33
RXA TXA DTRA# RTSA# MFA# RXRDYA# INTA VCC TXRDYB# RIB# CDB# DSRB#
XR16L2552 48-pin TQFP
32 31 30 29 28 27 26 25
44-PLCC PACKAGE
39 38 37 36
RX A T XA DT RA # RT S A #
XTAL 1 11 G ND 12 XTAL 2 13 A1 14 A2 15 CHS EL 16 INTB 17
35 M FA #
X R 16 L 25 52 4 4- pin PLCC
34 33 32 31
INTA V CC T X RDY B # RIB #
30 CDB # 29 DS R B #
XR16L2552 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. P1.0.3
PRELIMINARY
PIN DESCRIPTIONS
Pin Description
NAME 48-TQFP 44-PLCC TYPE PIN# PIN # DESCRIPTION
DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 10 9 4 3 2 1 48 47 46 45 44 20 10 14 15 9 8 7 6 5 4 3 2 24 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/O utput Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/O utput Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the L2552. Channel Select - UART channel A or B is selected by the logical state of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A3. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS# is low. It is especially useful during the initialization routine. UART channel A Interrupt output (active high). A logic high indicates channel A is requesting for service. UART channel B Interrupt output (active high). A logic high indicates channel B is requesting for service. UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. If it is not used, leave it unconnected. UART channel A Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel A. This pin is only available on the 48pin TQFP package. If it is not used, leave it unconnected. UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. If it is not used, leave it unconnected.
IOW#
15
20
I
CS#
13
18
I
CHSEL
11
16
I
INTA INTB TXRDYA#
30 12 43
34 17 1
O O O
RXRDYA#
31
-
O
TXRDYB#
28
32
O
3
rx rx rx rx
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