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Details, datasheet, quote on part number:XR16L2750
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Datasheet text preview:
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SEPTEMBER 2002
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
GENERAL DESCRIPTION
The XR16L27501 (2750) is a low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device operates from 2.25 to 5.5 Volt supply range and is pin-to-pin compatible to Exar's ST16C2550 and XR16C2850 except the 48-TQFP package. The 2750 register set is compatible to the ST16C2550 and the XR16C2850 enhanced features. It supports the Exar's enhanced features of 64 bytes of TX and RX FIFOs, programmable FIFO trigger level and FIFO level counters, automatic hardware (RTS/CTS) and software flow control, automatic RS-485 half duplex direction control output and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 6.25 Mbps at 5 Volt and 8X sampling clock. The 2750 is available in 48-pin TQFP and 44-pin PLCC packages.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
FEATURES
· 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Pin-to-pin compatible to Exar's ST16C2550 and
TI's TL16C752B on the 48-TQFP package
· Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
· Two independent UART channels
s s
s s s s s s s
s s s
APPLICATIONS
· Por table Appliances · Telecommunication Network Routers · Ethernet Network Routers · Cellular Data Devices · Factor y Automation and Process Controls
FIGURE 1. XR16L2750 BLOCK DIAGRAM
Reg set compatible to 16C2550 and 16C2850 Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt, and 3 Mbps at 2.5 Volt with 8X sampling rate Transmit and Receive FIFOs of 64 bytes Programmable TX and RX FIFO Trigger Levels Transmit and Receive FIFO Level Counters Automatic Hardware (RTS/CTS) Flow Control Selectable Auto RTS Flow Control Hysteresis Automatic Software (Xon/Xoff) Flow Control Automatic RS-485 Half-duplex Direction Control Output via RTS# Wireless Infrared (IrDA 1.0) Encoder/Decoder Automatic sleep mode Full modem interface
· Device Identification and Revision · Cr ystal oscillator or external clock input · Industrial and commercial temperature ranges · 48-TQFP and 44-PLCC packages
A 2 :A 0 D 7 :D 0 IO R # IO W # CSA# CSB# IN T A IN T B TXRDYA# TXRDYB# R XR D YA # R XR D YB # Reset 8 - b i t Data Bu s In te rfa c e
* 5 Volt Tolerant Inputs
2 . 2 5 to 5.5 Volt VCC GND
U A R T Channel A U AR T Regs BR G T X B , RXB, DTRB#, D S R B # , RTSB#, C T S B # , CDB#, RIB#, OP2B# XT AL1 XT AL2
2750BLK
6 4 Byte TX FIFO T X & RX IR EN D EC
T X A , RXA, DTRA#, D S R A # , RTSA#, D T S A # , CDA#, RIA#, OP2A#
U A R T Channel B ( s a m e as Channel A)
C r y s t a l Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
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FIGURE 2. PIN OUT ASSIGNMENT
XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
T XRD YA#
DS RA #
V CC
RI A#
CT S A # 38
CD A#
48
45
43
42
41
40
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D5 D6 D7 RX B RX A T XRD YB# T XA T XB O P 2B #
1 2 3 4 5 6 7 8 9
36 35 34 33
RE S E T DT R B # DT R A # RT S A # O P 2A # RXRD YA# IN T A IN T B A0 A1 A2 NC
XR 1 6 L 2 7 5 0 48-pin TQFP
32 31 30 29 28 27 26 25
CS A # 10 CS B # 11 NC 12 15 13 18 19 20 22 16 14 17 21 23 CT S B # 24 NC
RXRD YB#
DS RB #
T XR D YA #
RT S B #
X T A L2
CD B#
X T A L1
IO W #
IO R #
RI B#
G ND
D SR A # 41
44
43
42
40 39 38 37 36
6
5
4
3
2
D5 D6 D7 R XB R XA T X R D YB # TX A TX B O P 2B# C SA # C SB #
7 8 9 10 11 12 13 14 15 16 17 XT AL 1 18 XT AL 2 19 IO W # 20 C D B# 21 G N D 22 R XR D YB# 23 IO R # 2 4 D SR B # 25 R IB# 26 R T SB# 27 C T SB# 28
1
C TSA#
C D A#
R IA#
VC C
D4
D3
D2
D1
D0
R ES ET DTRB# DTRA# R T S A#
35 O P 2A#
XR16 L275 0 44- pin PLCC
34 33 32 31
R X R D YA # IN T A IN T B A0
30 A1 29 A2
ORDERING INFORMATION
PART NUMBER XR16L2750CJ XR16L2750IJ XR16L2750CM XR16L2750IM PACKAGE 44-PLCC 44-PLCC 48-TQFP 48-TQFP OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C
2
XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
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PIN DESCRIPTIONS
Pin Description
NAME 44-PLCC PIN # 48-TQFP PIN # TYPE DESCRIPTION
DATA BUS INTERFACE A2:A0 D7:D0 29, 30, 31 9, 8, 7, 6, 5, 4, 3, 2 24 26, 27, 28 3, 2, 1, 48, 47, 46, 45, 44 19 I I/O Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional).
IOR#
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART channel A select (active low) to enable UART channel A in the device for data bus operation. UART channel B select (active low) to enable UART channel B in the device for data bus operation. UART channel A Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0 (default). See MCR[3]. UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0 (default). See MCR[3].
IOW#
20
15
I
CSA# CSB# INTA
16 17 33
10 11 30
I I O
INTB
32
29
O
TXRDYA#
1
43
O
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2. If it is not used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel A. See Table 2. If it is not used, leave it unconnected. UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See Table 2. If it is not used, leave it unconnected. UART channel B Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel B. See Table 2. If it is not used, leave it unconnected.
RXRDYA#
34
31
O
TXRDYB#
12
6
O
RXRDYB#
23
18
O
3
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