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Details, datasheet, quote on part number:XR16L2751
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Datasheet text preview:
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SEPTEMBER 2002
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
GENERAL DESCRIPTION
The XR16L27511 (2751) is a low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device includes 2 additional capabilities over the XR16L2750: Intel and Motorola data bus selection and a "PowerSave" mode to further reduce sleep current to a minimum during sleep mode. The 2751's register set is compatible to the ST16C2550 and XR16C2850 but with added functions. It supports the Exar's enhanced features of 64 bytes of TX and RX FIFOs, programmable FIFO trigger level, FIFO level counters, automatic hardware and software flow control, automatic RS-485 half duplex direction control with programmable turn-around delay, and a complete modem interface. Onboard registers provide the user with operational status and data error tags. An internal loopback capability allows onboard diagnostics. Independent programmable baud rate generator is provided in each UART channel to support data rates up to 6.25 Mbps.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
FEATURES
· 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Functionally Compatible to ST16C2550 and
XR16C2850 with 4 additional inputs
· Intel or Motorola Data Bus Interface Select · Two Independent UARTs
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APPLICATIONS
Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt, and 3 Mbps at 2.5 Volt with 8X sampling rate 64 bytes of Transmit and Receive FIFOs Transmit and Receive FIFO Level Counters Programmable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Selectable RTS Flow Control Hysteresis. Automatic Software (Xoff/Xon) Flow Control Automatic RS-485 2-wire Half-duplex Direction Control to the Transceiver via RTS# Full Modem Interface Infrared Receive and Transmit Encoder/ decoder
· Por table and Battery Operated Appliances · Wireless Access Servers · Ethernet Network Routers · Cellular Data Devices · Telecommunication Network Routers · Factor y Automation and Process Controls
FIGURE 1. XR16L2751 BLOCK DIAGRAM
· PowerSave Feature reduces sleep current to 15 µA
at 3.3 Volt
· Device Identification · Cr ystal or external clock input · Industrial and Commercial Temperature ranges · 48 TQFP Package (7 x 7 x 1.0 mm)
Pw rSave A2:A0 D7 :D0 IOR# (VCC) IOW # (R/W#) CS A# (CS#) CS B# (A3) IN TA (IRQ#) IN TB (logic 0) TXR DYA# TXR DYB# RX RDYA # RX RDYB # Reset (Reset#) 1 6 /6 8 # CL KS EL HD CNT L # Intel or M o t o ro l a Data Bus In t e rf a c e
*5 Volt Tolerant Inputs
2.25 to 5.5 Volt VCC GN D
UA RT Channel A UA RT Re g s BR G 64 Byte TX FIFO TX & RX IR EN DEC TXA, RXA, DTRA#, DS RA#, RTSA#, DTS A#, CDA#, RIA#, OP 2 A #
64 Byte RX FIFO TXB, RXB, DTRB#, DS RB#, RTSB#, CTS B#, CDB#, RIB#, OP 2 B # XTAL1 XTAL2
UA RT Channel B (same as Channel A)
Crystal Osc/Buffer
2751BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
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FIGURE 2. PIN OUT ASSIGNMENT
XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
TX RDY A #
48
47
46
45
44
43
42
41
40
39
38
37
HDCNTL#
D SR A #
CDA #
V CC
D4
D3
D2
D1
D0
C T S A#
R IA #
D5 D6 D7 RXB RXA TXRDYB # TXA TXB O P 2 B# C SA # C SB # P W RS AV E
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32
R ES E T DTRB # DTRA # R T S A# O P 2 A# RXRDYA # INTA INTB A0 A1 A2 CLKS E L
XR16L 2751 48-pin TQFP (16 Mode )
31 30 29 28 27 26 25
R XR D Y B#
R T S B#
C T S B#
X T A L1
X T A L2
CDB #
D SR B #
16 /6 8#
I OW #
GN D
I OR #
R IB #
V CC
TXRDYA#
48
47
46
45
44
43
42
41
40
39
38
37
HDCNTL#
DSRA#
CDA#
VCC
D4
D3
D2
D1
D0
CTSA#
RIA#
D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP2B# CS# A3 PWRSAVE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32
RESET# DTRB# DTRA# RTSA# OP2A# RXRDYA# IRQ# INTB A0 A1 A2 CLKSEL
XR16L2751 48-pin TQFP (68 Mode )
31 30 29 28 27 26 25
XTAL1
XTAL2
RXRDYB#
CTSB#
CDB#
GND
RIB#
DSRB#
RTSB#
16/68#
R/W#
VCC
GND
ORDERING INFORMATION
PART NUMBER XR16L2751CM XR16L2751IM PACKAGE 48-TQFP 48-TQFP OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C
2
XR16L2751 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
REV. 1.0.0
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PIN DESCRIPTIONS
Pin Description
NAME 48-TQFP PIN # TYPE DESCRIPTION
DATA BUS INTERFACE A2:A0 D7:D0 IOR# (VCC) 26,27,28 3, 2, 1, 48, 47, 46, 45, 44 19 I I/O I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used and should be connected to VCC. When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the Motorola bus interface. When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is at logic 0, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel A interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation. When 16/68# pin is at logic 1 for Intel bus interface, this output becomes channel B interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output is not used and will stay at logic zero level. Leave this output unconnected. UART channel A Transmitter Ready (active low). The output provides the TX FIFO/ THR status for transmit channel A.
IOW# (R/W#)
15
I
CSA# (CS#)
10
I
CSB# (A3)
11
I
INTA (IRQ#)
30
O
INTB
29
O
TXRDYA#
43
O
3
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