|
Details, datasheet, quote on part number:XR16L2752
| |
Datasheet text preview:
áç áç
SEPTEMBER 2002
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
GENERAL DESCRIPTION
The XR16L27521 (2752) is a low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device operates from 2.25 to 5.5 Volt supply range and is pin-to-pin compatible to Exar's ST16C2552 and XR16C2852. The 2752 register set is compatible to the ST16C2552 and the XR16C2852 enhanced features. It supports the Exar's enhanced features of 64 bytes of TX and RX FIFOs, programmable FIFO trigger level and FIFO level counters, automatic hardware (RTS/CTS) and software flow control, automatic RS-485 half duplex direction control output and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 6.25 Mbps at 5 Volt and 8X sampling. The 2752 is available in the 44-pin PLCC package.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205
FEATURES
· 2.25 to 5.5 Volt Operation · 5 Volt Tolerant Inputs · Pin-to-pin compatible to Exar's ST16C2552 and
XR16C2852
· Improved version of PC16C552 · Two independent UART channels
s s
s s s s s s s
s s s
APPLICATIONS
· Por table Appliances · Telecommunication Network Routers · Ethernet Network Routers · Cellular Data Devices · Factor y Automation and Process Controls
FIGURE 1. XR16L2752 BLOCK DIAGRAM
Reg set compatible to 16C2552 and 16C2852 Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt and 3 Mbps at 2.5 Volt with 8X sampling rate Transmit and Receive FIFOs of 64 bytes Programmable TX and RX FIFO Trigger Levels Transmit and Receive FIFO Level Counters Automatic Hardware (RTS/CTS) Flow Control Selectable Auto RTS Flow Control Hysteresis Automatic Software (Xon/Xoff) Flow Control Automatic RS-485 Half-duplex Direction Control Output via RTS# Wireless Infrared (IrDA 1.0) Encoder/Decoder Automatic sleep mode Full modem interface
· Alter nate Function Register · Device Identification and Revision · Cr ystal oscillator or external clock input · Industrial and commercial temperature ranges · 44-PLCC package
A 2: A 0 D7:D0 I OR # I OW # CS# CHSEL INTA INTB TXRDYA# TXRDYB# MFA#
(OP2A#, BAUDOUTA#, or RXRDYA#)
*5 Volt Tolerant Inputs
2.25 V to 5 V VCC GND
UART Channel A UART Reg s BRG 8-bit Data B us I nt er f ac e 64 Byte TX FIFO TX & RX IR ENDEC RXA (or RXIRA) TXB (or TXIRB) RXB (or RXIRB) Crystal Osc/Buffer Modem Control Logic XTAL1 XTAL2 CTS#A/B, RI#A/B, CD#A/B, DSR#A/B DTR#A/B, RTS#A/B
2752BLK
TXA (or TXIRA)
64 Byte RX FIFO
UART Channel B (same as Channel A)
MFB#
(OP2B#, BAUDOUTB#, or RXRDYB#)
R e s et
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
áç áç
FIGURE 2. PIN OUT ASSIGNMENT
XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
TX R D Y A #
D SRA# 41
44
43
42
40
6
5
4
3
2
1
C TS A #
C DA#
R IA #
VC C
D4
D3
D2
D1
D0
D5 D6 D7 A0 XTAL1
7 8 9 10 11
39 38 37 36
R XA TXA D TRA # R TSA#
3 5 MF A#
G ND 12 XTAL2 A1 13 14
XR 1 6L 27 52 4 4-pin PLCC
34 33 32 31
IN T A VC C T X R D YB # R IB #
A2 15 C HSEL 16
30 C DB# 29 C S# 18 MFB# 19 IO W # 2 0 R ESET 21 G ND 22 R TS B # 2 3 IO R # 2 4 R XB 25 TX B 2 6 D TR B # 2 7 C TS B # 2 8 D SRB#
IN T B 1 7
ORDERING INFORMATION
PART NUMBER XR16L2752CJ XR16L2752IJ PACKAGE 44-PLCC 44-PLCC OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C
2
XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
áç
PIN DESCRIPTIONS
Pin Description
NAME 44-PLCC PIN # TYPE DESCRIPTION
DATA BUS INTERFACE A2:A0 D7:D0 IOR# 15, 14, 10 9, 8, 7, 6, 5, 4, 3, 2 24 I I/O I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2752. Channel Select - UART channel A or B is selected by the logical state of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS# is low. It is especially useful during the initialization routine. UART channel A Interrupt output (active high). A logic high indicates channel A is requesting for service. For more details, see Figures 18- 23. UART channel B Interrupt output (active high). A logic high indicates channel B is requesting for service. For more details, see Figures 18- 23.
IOW#
20
I
CS#
18
I
CHSEL
16
I
INTA INTB TXRDYA# TXRDYB#
34 17 1 32
O O O O
UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2.
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/ THR status for transmit channel B. See Table 2. Multi-Function Output Channel A. This output pin can function as the OP2A#, BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the Alternate Function Register (AFR). These signal functions are described as follows: 1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0 when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a logic 1 condition after a reset or power-up. 2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate clock output is available at this pin. 3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data transfers. See Table 2 for more details.
MODEM OR SERIAL I/O INTERFACE MFA# 35 O
3
|
|
