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Details, datasheet, quote on part number:XRT7295
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| Part: | XRT7295 |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Line Interfaces |
| Description: | DS3/STS-1/Sonet Integrated Line Receiver Manual |
| Company: | Exar Corporation |
| Datasheet: | Download XRT7295 datasheet File size : 232 kB |
| Request For quote: | Find where to buy XRT7295
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Datasheet text preview:
XR-T7295
...the analog plus company TM
DS3/Sonet STS-1 Integrated Line Receiver
June 1997-3
FEATURES D Fully Integrated Receive Interface for DS3 and STS-1 Rate Signals D Integrated Equalization (Optional) and Timing Recovery D Loss-of-Signal and Loss-of-Lock Alarms D Variable Input Sensitivity Control D 5V Power Supply D Pin Compatible with XR-T7295E D Companion Device to T7296 Transmitter
APPLICATIONS D Interface to DS-3 Networks D Digital Cross-Connect Systems D CSU/DSU Equipment D PCM Test Equipment D Fiber Optic Terminals
GENERAL DESCRIPTION The XR-T7295 DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1 (51.84Mbps) signal transmitted over coaxial cable. (See Figure 13). The device also provides the functions of receive equalization (optional), automatic-gain control (AGC), clock-recovery and data retiming, loss-of-signal and loss-of-frequency-lock detection. The digital system interface is dual-rail, with received positive and negative 1s appearing as unipolar digital signals on separate output leads. The on-chip equalizer is designed for cable distances of 0 to 450ft. from the cross-connect frame to the device. The receive input has a variable input sensitivity control, providing three different sensitivity ORDERING INFORMATION
Operating Temperature Range -40╟C to + 85╟C -40╟C to + 85╟C
settings, to adapt longer cables. High input sensitivity allows for significant amounts of flat loss within the system. Figure 1 shows the block diagram of the device. The XR-T7295 device is manufactured using linear CMOS technology. The XR-T7295 is available in either a 20-pin plastic DIP or 20-pin plastic SOJ package for surface mounting. Two versions of the chip are available, one is for either DS3 or STS-1 operation (the XR-T7295, this data sheet), and the other is for E3 operation (the XR-T7295E, refer to the XR-T7295E data sheet). Both versions are pin compatible. For either DS3 or STS-1, an input reference clock at 44.736MHz or 51.84MHz provides the frequency reference for the device.
Part No. XR-T7295IP XR-T7295IW
Package 20 Lead 300 Mil PDIP 20 Lead 300 Mil JEDEC SOJ
Rev. 1.05
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-T7295
BLOCK DIAGRAM
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REQB 18 4 5 20 1 11 9 12 10 2 Attenuator Gain & Equalizer Slicers Phase Detector Loop Filter VCO RIN Retimer Peak Detector 19 AGC Frequency Phase Aquisition Circuit Digital LOS Detector LOSTHR Analog LOS Analog LOS 7 Equalizer Tuning Ckt. 17 3 6 13 8 ICT TMC1 TMC2 EXCLK RLOL
LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC
14 RCLK
16 RPDATA 15 RNDATA
RLOS
Figure 1. Block Diagram
Rev. 1.05 2
XR-T7295
PIN CONFIGURATION
GNDA R IN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VDDA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK VDDC VDDD
GNDA R IN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDDA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK VDDC VDDD
20 Lead PDIP (0.300")
20 Lead SOJ (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3,6 4,5 7 8 9 10 11 12 13 Symbol GNDA RIN TMC1-TMC2 LPF1-LPF2 RLOS RLOL GNDD GNDC VD D D VD D C EXCLK I Type I I I O O Description Analog Ground. Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series with 50 k. Test Mode Control 1 and 2. Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. PLL Filter 1 and 2. An external capacitor (0.1╣F $20%) is connected between these pins. Receive Loss-of-signal. This pin us set high on loss of the data signal at the receive input. (See Table 7) Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock. Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with PLL clock. Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with EXCLK. 5V Digital Supply ($10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 5V Digital Supply ($10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. External Reference Clock. A valid DS3 (44.736MHz $100ppm) or STS-1 (51.84MHz + 100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD /2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns. Receive Clock. Recovered clock signal to the terminal equipment. Receive Negative Data. Negative pulse data output to the terminal equipment. (See Figure 11.) Receive Positive Data. Positive pulse data output to the terminal equipment. (See Figure 11) In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-circuit testing. There is an internal pull-up on this pin. Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low places the equalizer in the data path. Loss-of-signal Threshold Control. The voltage forced on this pin controls the input lossof-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin must be set to the desired level upon power-up and should not be changed during operation. 5V Analog Supply ($10%).
14 15 16 17
RCLK RNDATA RPDATA ICT
O O O I
18 19
REQB LOSTHR
I I
20
VD D A
Rev. 1.05 3
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