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Details, datasheet, quote on part number:XRT7295AE
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Datasheet text preview:
DS3/Sonet STS-1 Integrated Line Receiver
December 2000-2
XRT7295AE
FEATURES D Fully Integrated Receive Interface for DS3 and STS-1 Rate Signals D Integrated Equalization (Optional) and Timing Recovery D Loss-of-Signal and Loss-of-Lock Alarms D Variable Input Sensitivity Control D 5V Power Supply D Pin Compatible with XRT7295AT D Companion Device to T7296 Transmitter
APPLICATIONS D Interface to DS-3 Networks D Digital Cross-Connect Systems D CSU/DSU Equipment D PCM Test Equipment D Fiber Optic Terminals
GENERAL DESCRIPTION The XRT7295AE DS3/SONET STS-1 integrated line receiver is a fully integrated receive interface that terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1 (51.84Mbps) signal transmitted over coaxial cable. (See Figure 13). The device also provides the functions of receive equalization (optional), automatic-gain control (AGC), clock-recovery and data retiming, loss-of-signal and loss-of-frequency-lock detection. The digital system interface is dual-rail, with received positive and negative 1s appearing as unipolar digital signals on separate output leads. The on-chip equalizer is designed for cable distances of 0 to 450ft. from the cross-connect frame to the device. The receive input has a variable input sensitivity control, providing three different sensitivity ORDERING INFORMATION
Operating Temperature Range -40°C to + 85°C
settings, to adapt longer cables. High input sensitivity allows for significant amounts of flat loss within the system. Figure 1 shows the block diagram of the device. The XRT7295AE device is manufactured using linear CMOS technology. The XRT7295AE is available in a 20-pin plastic SOJ package for surface mounting. Two versions of the chip are available, one is for either DS3 or STS-1 operation (the XRT7295AE, this data sheet), and the other is for E3 operation (the XRT7295AT, refer to the XRT7295AT data sheet). Both versions are pin compatible. For either DS3 or STS-1, an input reference clock at 44.736MHz or 51.84MHz provides the frequency reference for the device.
Part No. XRT7295AEIW
Package 20 Lead 300 Mil JEDEC SOJ
Rev. 1.20
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
XRT7295AE
BLOCK DIAGRAM
LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC 4 5 20 1 11 9 12 10
REQB 18
2 RIN
Attenuator
Gain & Equalizer
Slicers
Phase Detector
Loop Filter
VCO
14 RCLK
Retimer Peak Detector
16 RPDATA 15 RNDATA
19 LOSTHR
AGC
Frequency Phase Aquisition Circuit
Digital L OS Detector
Analog L OS
Equalizer Tuning Ckt.
Analog L OS
7
RLOS
17 ICT
3 TMC1
6 TMC2
13 EXCLK
8 RLOL
Figure 1. Block Diagram
Rev.1.20 2
XRT7295AE
PIN CONFIGURATION
GNDA RIN TMC1 LPF1 LPF2 TMC2 RLOS RLOL GNDD GNDC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
V D DA LOSTHR REQB ICT RPDATA RNDATA RCLK EXCLK V D DC V D DD
20 Lead SOJ (Jedec, 0.300") PIN DESCRIPTION
Pin # 1 2 3 ,6 4 ,5 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol GNDA RIN TMC1-TMC2 LPF1-LPF2 RLOS RLOL GNDD GNDC VDDD VDDC EXCLK RCLK RNDATA RPDATA ICT REQB LOSTHR I O O O I I I Type I I I O O Description Analog Ground. Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series with 50 kW. Test Mode Control 1 and 2. Internal test modes are enabled within the device by using TMC1 and TMC2. Users must tie these pins to the ground plane. PLL Filter 1 and 2. An external capacitor (0.1mF ±20%) is connected between these pins. Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input. (See Table 6) Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock. Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with PLL clock. Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with EXCLK. 5V Digital Supply (±10%) for PLL Clock. Power for all circuitry running synchronously with PLL clock. 5V Digital Supply (±10%) for EXCLK. Power for all circuitry running synchronously with EXCLK. External Reference Clock. A valid DS3 (44.736MHz ±100ppm) or STS-1 (51.84MHz + 100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD /2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns. Receive Clock. Recovered clock signal to the terminal equipment. Receive Negative Data. Negative pulse data output to the terminal equipment. (See Figure 11.) Receive Positive Data. Positive pulse data output to the terminal equipment. (See Figure 11) In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-circ u i t t e s t i n g . T h e re i s a n i n t e rn a l p u l l -u p o n t h i s p i n . Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low p l a c e s th e e q u a l i z e r i n th e d a ta p a th . Loss-of-signal Threshold Control. The voltage forced on this pin controls the input lossof-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin must be set to the desired level upon power-up and should not be changed during operati o n . 5V Analog Supply (±10%).
20 Rev.1.20
VDDA
3
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