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Details, datasheet, quote on part number:XRT72L13
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| Part: | XRT72L13 |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Multiplexers/demultiplexers |
| Description: | Multiplexer/framer ic |
| Company: | Exar Corporation |
| Datasheet: | Download XRT72L13 datasheet File size : 4527 kB |
| Request For quote: | Find where to buy XRT72L13
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Datasheet text preview:
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SEPTEMBER 2000
PRELIMINARY
XRT72L13
REV. P1.0.5
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
GENERAL DESCRIPTION
The XRT72L13 is a fully integrated, low power, Multiplexer/Framer IC which performs Multiplexing/Demutiplexing of 28 DS1or 21 E1 signals into/from a DS3 signal with either M13 or C-bit parity frame format, performs Clear Channel DS3 Framing, and suppor ts High speed HDLC/LAPD data linking. The XRT72L13 also contains M12 and M23 bit-interleaving multiplexing/demultiplexing functions with necessary stuffing and destuffing control. Seven internal DS2/G.747 framers are included to support Mux/Demux purposes. The XRT72L13 contains an integral DS3 Framer which provides Clear Channel DS3 Framing and Error Accumulation in accordance with ANSI/ITU-T specifications. The XRT72L13 provides the intelligent functions of DS3/DS2 mode control, signaling control, error and alarm reporting and handles the HDLC/LAPD data link through internal registers accessible via an 8-bit parallel, memory mapped, µProcessor interface. FEATURES
· A fully integrated device that supports: Multiplexing/Demultiplexing Mode Clear Channel DS3 Framer Mode High Speed HDLC Controller Mode · Suppor ts Multiple Loop-back modes · Smooths gapped clock signals · Suppor ts Intel or Motorola PIO µP interfaces · Available in a 208 pin PQFP package · Single 3.3V Power Supply · 5V Tolerant I/O · Operates over the Industrial Temperature Range APPLICATIONS · M13 Multiplexer/Demuliplexer Applications. · Frame Relay Systems · Digital Access and Cross Connect Systems · Local Digital Switch · Add/Drop Multiplexers · DS3 Data/Channel Service Units. · Test Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L13 MULTIPLEXER/FRAMER
TxHDLC TtrollLC ConxHDer Controller
TxHDLC[0:7] TxHDLCClk Send_FCS
TxDS1[0:27]
TxPOS TxNEG TxLine Clk
M23 M2 MUX 3 MUX
M12 M1 MUX 2 MUX
TxClk[0:27]
Clear Channel Cl 3 r Channel DSeaFramer DS3 Framer
RxPOS RxNEG RxLine Clk
DS2 or G.747 Data Streams
32/64 Bit De-Jitter FIFO
M23 M23 DEMUX DEMUX
M12 DEMUX
RxDS1[0:27]
RxClk[0:27]
Microprocessor Mictrerpaocessor In o f r ce Interface
RxHDLC CoRtrHDer n x oll LC Controller
RxHdlc[0:7] RxHDLCClk RxIdle Valid-FCS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRT72L13 M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.5
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PRELIMINARY
PIN OUT OF THE 72L13 FRAMER IC
TxFrame TxInClk TxNibFrame TxOHInd/TxPLClkEnb TxNibClk TxNib_0/TxSer TxNib_1 V DD TxNib_2 TxNib_3 TxOHIns TxAISEn TxOHFrame TxOHEnable TxOHClk TxO H TxNE G TxP O S TxLineClk REQB TAOS G ND E NCO DIS TxL E V RLOOP LLOOP DMO RLOL E xtL O S V DD RxV CO u p RxVCOdown RxLineClk RxP O S RxNE G RxO H RxOHEnable RxOHClk RxOHFrame RxL O S RxNib_3/RxRed RxNib_2/RxAIS RxNib_1/RxOOF G ND RxNib_0/RxSer RxOutClk RxOHInd/RxPLClkEnb RxClk RxFrame RxInClk RxDS 1 Da ta _ 2 7 RxDS1Clk_27 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
RxDS1Data_26 RxDS1Clk_26 RxDS1Data_25 RxDS1Clk_25 RxDS1Data_24 RxDS1Clk_24 RxDS1Data_23 RxDS1Clk_23 RxDS1Data_22 RxDS1Clk_22 VDD RxDS1Data_21 RxDS1Clk_21 RxDS1Data_20 RxDS1Clk_20 RxDS1Data_19 RxDS1Clk_19 RxDS1Data_18 RxDS1Clk_18 RxDS1Data_17 RxDS1Clk_17 RxDS1Data_16 RxDS1Clk_16 RxDS1Data_15 TCK TMS TDI TDO GND RxDS1Clk_15 RxDS1Data_14 RxDS1Clk_14 RxDS1Data_13 RxDS1Clk_13 RxDS1Data_12 RxDS1Clk_12 RxDS1Data_11 RxDS1Clk_11 VDD RxDS1Data_10 RxDS1Clk_10 RxDS1Data_9 RxDS1Clk_9 RxDS1Data_8 RxDS1Clk_8 RxDS1Data_7/RxHDLC_Data_7 RxDS1Clk_7 RxDS1Data_6/RxHDLC_Data_6 GND RxDS1Clk_6 RxDS1Data_5/RxHDLC_Data_5 RxDS1Clk_5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 Lead PQFP
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
TxFrameRef DS2OutClk DS2InClk TxDS1Clk_0 TxDS1Data_0 TxDS1Clk_1 TxDS1Data_1 TxDS1Clk_2 TxDS1Data_2 TxDS1Clk_3 GND TxDS1Data_3 TxDS1Clk_4 TxDS1Data_4 TxDS1Clk_5 TxDS1Data_5 TxDS1Clk_6 TxDS1Data_6 TxDS1Clk_7 VDD TxDS1Data_7 TxDS1Clk_8 TxDS1Data_8 TxDS1Clk_9 TxDS1Data_9 TxDS1Clk_10 TxDS1Data_10 TxDS1Clk_11 GND TxDS1Data_11 TxDS1Clk_12 TxDS1Data_12 TxDS1Clk_13 TxDS1Data_13 TxDS1Clk_14 TxDS1Data_14 TxDS1Clk_15 TxDS1Data_15 VDD TxDS1Clk_16 TxDS1Data_16 TxDS1Clk_17 TxDS1Data_17 TxDS1Clk_18 TxDS1Data_18 TxDS1Clk_19 TxDS1Data_19 TxDS1Clk_20 TxDS1Data_20/TxHDLCData_0 TxDS1Clk_21 TxDS1Data_21/TxHDLCData_1 TxDS1Clk_22
ORDERING INFORMATION
PART # XRT72L13IQ PACKAGE 208 pin PQFP OPERATING TEMPERATURE -40°C to +85°C
RxDS1Data_4/RxHDLC_Data_4 RxDS1Clk_4 RxDS1Data_3/RxHDLC_Data_3 RxDS1Clk_3/RxIDLE RxDS1Data_2/RxHDLC_Data_2 RxDS1Clk_2/ValidFCS RxDS1Data_1/RxHDLC_Data_1 RxDS1Clk_1/RxHDLCClk RxDS1Data_0/RxHDLC_Data_0 VDD RxDS1Clk_0/TxHDLCClk RESETB A0 D0 A1 INTB* D1 A2 MOTO GND D2 A3 Rdy_Dtck D3 A4 ALE_AS D4 A5 CSB D5 A6 RdB_DS D6 A7 VDD WRB_RW D7 A8 GND (TEST MODE) NIBBLEINTF TxDS1Data_27/TxHDLCData_7 TxDS1Clk_27/SEND_MSG TxDS1Data_26/TxHDLCData_6 TxDS1Clk_26/SEND_FCS TxDS1Data_25/TxHDLCData_5 GND TxDS1Clk_25 TxDS1Data_24/TxHDLCData_4 TxDS1Clk_24 TxDS1Data_23/TxHDLCData_3 TxDS1Clk_23 TxDS1Data_22/TxHDLCData_2
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.5
TABLE OF CONTENTS
GENERAL DESCRIPTION ........ 1
FEATURES ...... APPLICATIONS ........ Figure 1. Block Diagram of the XRT72L13 Multiplexer/Framer .. PIN OUT OF THE 72L13 FRAMER IC ...... ORDERING INFORMATION .... 1 1 1 2 2
ELECTRICAL CHARACTERISTICS ......... 49
ABSOLUTE MAXIMUMS .............. 49 DC ELECTRICAL CHARACTERISTICS ... 49 AC ELECTRICAL CHARACTERISTICS ... 49 AC ELECTRICAL CHARACTERISTICS (CONT.) ..... 50 Figure 2. Timing Diagram for Transmit Payload Input Interface, when the XRT72L13 is operating in both the DS3 and Loop-Timing Modes ........ 53 Figure 3. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L13 is operating in both the DS3/Serial and Local-Timing Modes ....... 54 Figure 4. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L13 is operating in both the DS3/Nibble and Looped-Timing Modes .... 54 Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L13 is operating in the DS3/Nibble and Local-Timing Modes .. 55 Figure 6. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .... 55 Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .... 56 Figure 8. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the rising edge of "TxLineClk" ............ 56 Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the falling edge of "TxLineClk" ........... 57 Figure 10. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the rising edge of "RxLineClk" ...... 57 Figure 11. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the falling edge of "RxLineClk" ..... 58 Figure 12. Receive Payload Data Output Interface Timing (Serial Mode Operation) .... 58 Figure 13. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ............ 59 Figure 14. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ... 59 Figure 15. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ..... 60 Figure 16. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ........ 60 Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ....... 61 Figure 18. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ...... 61 Figure 19. Microprocessor Interface Timing - Intel Type Write Burst Access Operation ..... 62 Figure 20. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation .. 62 Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation .. 63 Figure 22. Microprocessor Interface Timing - Motorola Type Read Burst Access Operation ....... 63 Figure 23. Microprocessor Interface Timing - Motorola Type Write Burst Access Operation ....... 63 Figure 24. Microprocessor Interface Timing - ResetB* Pulse Width ...... 63 1.0 SYSTEM DESCRIPTION .......... 64 Figure 25. Block Diagram of the XRT72L13 M13 Multiplexer/Framer IC ......... 64
1.1 XRT72L13 OPERATION WHILE IN THE MULTIPLEXER/DE-MULTIPLEXER MODE ......... 64
Figure 26. Functional Block Diagram of the XRT72L13 M13 Multiplexer/Framer IC, while operating in the "Multiplexer/De-Multiplexer Mode ........... 65
1.1.1 In the Transmit Direction .... 65 1.1.2 In the Receive Direction ..... 66 1.1.3 Diagnostic Resources available for MUX/DEMUX Mode ............ 66
Figure 27. Illustration of the XRT72L13 Operating in the "DS1/E1 Tributary Loop-back Mode ..... 67 Figure 28. Illustration of the XRT72L13 Operating in the "DS2/ITU-T G.747 Tributary Loop-Back
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