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Details, datasheet, quote on part number:XRT72L52_CS
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JANUARY 2001
PRELIMINARY
XRT72L52
REV. P1.1.3
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
GENERAL DESCRIPTION
The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept "User Data" from the Terminal Equipment and insert this data into the "payload" bitfields within an "outbound" DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an "inbound" DS3/E3 Data Stream (from the Remote Terminal Equipment) and extract out the "User Data". The XRT72L52 DS3/E3 Framer device is designed to support full-duplex data flow between Terminal Equipment and an LIU (Line Interface Unit) IC. The Framer Device will transmit, receive and process data in the DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3ITU-T G.832 Framing Formats. The XRT72L52 DS3/E3 Framer IC consists of two Transmit sections, two Receiver sections, two Performance Monitor Sections and a Microprocessor interface. The Transmit Sections, include a Transmit Payload Data Input Interface, a Transmit Overhead data Input Interface Section, a Transmit HDLC Controller, a Transmit DS3/E3 Framer block and a Transmit LIU Interface Block which permits the Terminal Equipment to transmit data to a remote terminal. The Receive Sections, consist of a Receive LIU Interface, a Receive DS3/E3 Framer, a Receive HDLC Controller, a Receive Payload Data Output Interface, and a Receive Overhead Data Interface which allows FIGURE 1. BLOCK DIAGRAM OF THE XRT72L52
the local terminal equipment to receive data from remote terminal equipment. The Microprocessor Interface is used to configure the Framer IC in different operating modes and monitor the performance of the Framer. The Performance Monitor Sections consist of a large number of "Reset-upon-Read" and "Read-Only" registers that contain cumulative and "one-second" statistics that reflect the performance/health of the two channels of the Framer IC/system. FEATURES · Transmits, Receives and Processes data in the DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-ITU-T G.832 Framing Formats. · 2 Channel HDLC Controller - Tx and Rx · Interfaces to all Popular Microprocessors · Integrated Framer Performance Monitor · Available in a 160 Pin PQFP package · 3.3V Power Supply with 5V Tolerant I/O · Operating Temperature -40°C to +85°C AP PLICATIONS · Network Interface Units · CSU/DSU Equipment. · PCM Test Equipment · Fiber Optic Terminals · DS3/E3 Frame Relay Equipment
Reset TestMode NibbleLnTF TxOHEnable TxOHClk TxOHFrame TxAISEn TxOH TxOHIns
Typical Channel n Where n = 0 or 1
T3/E3 Transmit Overhead Interface
T3/E3 Transmit Framer
T3/E3 transmit Input
HDLC controller
TxOHInd[n:0] TxNibFrame[n:0] TxFrame[n:0] TxNibClk[n:0] TxLnClk[n:0] TxFrameRef[n:0] TxNib[n:0] TxSer[n:0]
TxLineClk[n:0] TxPOS[n:0] TxNEG[n:0] LIU Interface/ Controller T3 FEAC & Data Link Controller Performance Monitor Interrupt Controller uP Interface
RxLineClk[n:0] RxPOS[n:0] RxNEG[n:0] ExtLOS
A(11:0) D(7:0) ALE_AS WR_R/W CS RDY_DTCK Reset INT MOTO RD_DS
RxOHEnable[n:0] RxOHClk[n:0] RxOH[n:0] RxRed[n:0] RxOHFrame[n:0] RxOOF[n:0]
T3/E3 Receive Overhead Interface
T3/E3 Receive Framer
T3/E3 Receive Output
HDLC controller
RxClk[n:0] RxOHind[n:0] RxFrame[n:0] RxNib[n:0] RxSer[n:0] RxOUTClk[n:0]
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
áç
PRELIMINARY
FIGURE 2. PIN OUT OF THE XRT72L52
RxNib1[0]/RxHDLCDat1[0] RxNib2[0]/RxHDLCDat2[0] RxNib3[0]/RxHDLCDat3[0] NC Int Rdy_Dtck GND D(7) D(6) D(5) D(4) VDD D(3) D(2) D(1) D(0) GND A( 9) A( 8) A( 7) A( 6) A( 5) A( 4) A( 3) A( 2) A( 1) A( 0) NC ALE_AS WR_RW CS MOTO Reset NibbleIntf TestMode Rd_DS NC TxNib0[1]/TxHDLCDat0[1] TxNib1[1]/TxHDLCDat1[1] TxNib2[1]/TxHDLCDat2[1] RxNib0[0]/RxHDLCDat0[0] RxFrame[0] VDD RxOHInd[0] RxSer[0]/RxIdle[0] RxClk[0] GND TxFrame[0] TxNibFrame[0]/ValFCS[0] TxNIBClk[0]/SndFCS[0] TxOHInd[0]/TxHDLCDat6[0] GND TxSer[0]/SndMsg[0] TxNib3[0]/TxHDLCDat3[0] TxNib2[0]/TxHDLCDat2[0] TxNib1[0]/TxHDLCDat1[0] TxNib0[0]/TxHDLCDat0[0] TxAISEn[0] TxOH[0]/TxHDLCDat5[0] TxOHIns[0]/TxHDLCDat4[0] VDD TxOHEnable[0]/TxHDLCDat7[0] TxOHClk[0] TxOHFrame[0]/TxHDLCClk[0] RxOHEnable[0]/RxHDLCDat5[0] RxOHFrame[0]/RxHDLCDat4[0] RxOHClk[0]/RxHDLCClk[0] RxOH[0]/RxHDLCDat6[0] GND DMO[0] ExtLOS[0] RLOL[0] GND NC RLOOP[0] LLOOP[0] Req[0] TAOS[0] RxRed[0] RxAIS[0] 12 0 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
XRT72L52
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TxNib3[1]/TxHDLCDat3[1] TxSer[1]/SndMsg[1] GND TxOHInd[1]/TxHDLCDat6[1] TxNIBClk[1]/SndFCS[1] TxFrame[1] TxNibFrame[1]/ValFCS[1] RxFrame[1] RxSer[1]/RxIdle[1] VDD RxClk[1] RxNib0[1]/RxHDLCDat0[1] RxNib1[1]/RxHDLCDat1[1] RxNib2[1]/RxHDLCDat2[1] RxNib3[1]/RxHDLCDat3[1] RxOHInd[1] GND RxOHClk[1]/RxHDLCClk[1] RxOHEnable[1]/RxHDLCDat5[1] RxOHFrame[1]/RxHDLCDat4[1] RxOH[1]/RxHDLCDat6[1] TxOHClk[1] TxOHFrame[1]/TxHDLCClk[1] TxOHEnable[1]/TxHDLCDat7[1] VDD TxOHIns[1]/TxHDLCDat4[1] TxOH[1]/TxHDLCDat5[1] TxAISEn[1] GND TxLev[1] EncoDis[1] RxLOS[1] RxOOF[1] RxAIS[1] RxRed[1] TAOS[1] Req[1] LLOOP[1] RLOOP[1] GND
ORDERING INFORMATION
PART NUMBER XRT72L52 PACKAGE TYPE 28x28mm 160 lead QFP OPERATING TEMPERATURE RANGE -40°C to +85°C
VDD RxOOF[0] RxLOS[0] EncoDis[0] TxLev[0] GND NC TDI TCK NC TRST TMS GND TDO RxOutClk[0]RxHDLCDat7[0] TxNEG[0] TxPOS[0] TxLineClk[0] VDD TxFrameRef[0] RxNEG[0] TxInClk[0] RxPOS[0] RxLineClk[0] NC TxFrameRef[1] RxNEG[1] TxInClk[1] RxPOS[1] RxLineClk[1] GND TxLineClk[1] TxPOS[1] TxNEG[1] RxOutClk[1]/RxHDLCDat7[1] VDD NC DMO[1] ExtLOS[1] RLOL[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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áç áç
PRELIMINARY
XRT72L52
TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.3
TABLE OF CONTENTS
GENERAL DESCRIPTION ..... 1
....... .......... Figure 1. Block Diagram of the XRT72L52 ........... Figure 2. Pin Out of the XRT72L52 ........
FEATURES APPLICATIONS
1 1 1 2
ORDERING INFORMATION ........... 2 PIN DESCRIPTIONS ........ 3 ELECTRICAL CHARACTERISTICS ...... 24
ABSOLUTE MAXIMUMS ........... 24 DC ELECTRICAL CHARACTERISTICS ......... 24 AC ELECTRICAL CHARACTERISTICS ......... 24 AC ELECTRICAL CHARACTERISTICS (CONT.) ........... 26 1.0 Timing Diagrams ...... 30 Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L52 Device is operating in both the DS3 and Loop-Timing Modes ....... 30 Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L52 Device is operating in both the DS3 and Local-Timing Modes ............ 30 Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 Device is operating in both the DS3/Nibble and Looped-Timing Modes ..... 31 Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 Device is operating in the DS3/Nibble and Local-Timing Modes ........ 31 Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 32 Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 32 Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the rising edge of "TxLineClk" ............ 33 Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the falling edge of "TxLineClk" ........... 33 Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the rising edge of "RxLineClk" ............ 34 Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the falling edge of "RxLineClk" ........... 34 Figure 13. Receive Payload Data Output Interface Timing ......... 35 Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ....... 35 Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ....... 36 Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 36 Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ..... 37 Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ..... 37 Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ............ 38 Figure 20. Microprocessor Interface Timing - Intel type Write Burst Access Operation ..... 38 Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 39 Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 39 Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........ 40 2.0 The Microprocessor Interface Block ....... 41
2.1 CHANNEL SELECTION WITHIN THE XRT72L52 DEVICE ......... 41
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS A(9) AND THE SELECTED CONFIGURATION REGISTER BANK ............ 41 Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 42
2.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .... 42
TABLE 2: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND MOTOROLA MODES .......... 43 TABLE 3: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTERFACE IS OPERATING IN THE INTEL MODE ........ 43
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