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Details, datasheet, quote on part number:XRT72L58_CS
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Datasheet text preview:
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JANUARY 2001
PRELIMINARY
XRT72L58
REV. P1.1.2
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
GENERAL DESCRIPTION
The XRT72L58 Octal DS3/E3 Framer is designed to accept "User Data" from the Terminal Equipment and insert this data into the "payload" bit-fields within an "outbound" DS3/E3 Data Stream. Further, the Framer is also designed to receive an "inbound" DS3/E3 Data Stream (from the Remote Terminal Equipment) and extract out the "User Data". The XRT72L58 DS3/E3 Framer is designed to suppor t full-duplex data flow between Terminal Equipment and an LIU (Line Interface Unit) IC. The Framer will transmit, receive and process data in the DS3-Cbit Parity, DS3-M13, E3-ITU-T G.751 and E3-ITU-T G.832 Framing Formats. The XRT72L58 DS3/E3 Framer consists of Eight Transmit sections, Eight Receiver sections, Eight Performance Monitor Sections and a Microprocessor interface. The Transmit Sections, include a Transmit Payload Data Input Interface, a Transmit Overhead data Input Interface Section, a Transmit HDLC Controller, a Transmit DS3/E3 Framer block and a Transmit LIU Interface Block which permits the Terminal Equipment to transmit data to a remote terminal. The Receive Sections, consist of a Receive LIU Interface, a Receive DS3/E3 Framer, a Receive HDLC Controller, a Receive Payload Data Output Interface, and a Receive Overhead Data Interface which allows FIGURE 1. BLOCK DIAGRAM OF THE XRT72L58
the local terminal equipment to receive data from remote terminal equipment. The Microprocessor Interface is used to configure the Framer in different operating modes and monitor the performance of the Framer. The Performance Monitor Sections consist of a large number of "Reset-upon-Read" and "Read-Only" registers that contain cumulative and "one-second" statistics that reflect the performance/health of the Eight channels of the Framer/system. FEATURES · Transmits, Receives and Processes data in the DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-ITU-T G.832 Framing Formats. · 8 Channel HDLC Controller - Tx and Rx · Interfaces to all Popular Microprocessors · Integrated Framer Performance Monitor · Available in a 388 Ball PBGA package · 3.3V Power Supply with 5V Tolerant I/O · Operating Temperature -40°C to +85°C AP PLICATIONS · Network Interface Units · CSU/DSU Equipment. · PCM Test Equipment · Fiber Optic Terminals · DS3/E3 Frame Relay Equipment
Reset TestMode NibbleLnTF TxOHEnable TxOHClk TxOHFrame TxAISEn TxOH TxOHIns
Typical Channel n Where n = 0, 1, 2, 3, 4, 5, 6 & 7
T3/E3 Transmit Overhead Interface
T3/E3 Transmit Framer
T3/E3 transmit Input
HDLC controller
TxOHInd[n:0] TxNibFrame[n:0] TxFrame[n:0] TxNibClk[n:0] TxLnClk[n:0] TxFrameRef[n:0] TxNib[n:0] TxSer[n:0]
TxLineClk[n:0] TxPOS[n:0] TxNEG[n:0] LIU Interface/ Controller T3 FEAC & Data Link Controller Performance Monitor Interrupt Controller uP Interface
RxLineClk[n:0] RxPOS[n:0] RxNEG[n:0] ExtLOS
A(11:0) D(7:0) ALE_AS WR_R/W CS RDY_DTCK Reset INT MOTO RD_DS
RxOHEnable[n:0] RxOHClk[n:0] RxOH[n:0] RxRed[n:0] RxOHFrame[n:0] RxOOF[n:0]
T3/E3 Receive Overhead Interface
T3/E3 Receive Framer
T3/E3 Receive Output
HDLC controller
RxClk[n:0] RxOHind[n:0] RxFrame[n:0] RxNib[n:0] RxSer[n:0] RxOUTClk[n:0]
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRT72L58 EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
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PRELIMINARY
FIGURE 2. PIN OUT OF THE XRT72L58
( S e e pin list for pin names and function)
AF 1 AE 1 AD 1 AC 1 AB 1 AA 1 Y1 W1 V1 U1 T1 R1 P1 N1 M1 L1 K1 J1 H1 G1 F1 E1 D4 C1 B1 A1 D4 D 23 L2 L3 L4 G V1 V1 V1 V1 V3 G V1 V1 V1 V1 V3 G G G G G V3 G G G G G V3 G V2 V2 V2 V2 V3 G V2 V2 V2 V2 V3 L 23 L 24 L 25 T 23 T 24 T 25 AC 4 AC 23
AF 26
AF AE AD
AC 26
AC AB AA Y W V U
T 26
T2
T3
T4
T R P N M
L 26
L K J H G F E
XRT72L58
D 26
D C B
A 26
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ORDERING INFORMATION
PART NUMBER XRT72L58IB PACKAGE TYPE 35x35mm 388 Ball PBGA OPERATING TEMPERATURE RANGE -40°C to +85°C
2
áç áç
PRELIMINARY
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
TABLE OF CONTENTS
GENERAL DESCRIPTION ..... 1
FEATURES APPLICATIONS
....... .......... Figure 1. Block Diagram of the XRT72L58 ........... Figure 2. Pin Out of the XRT72L58 ........
1 1 1 2
ORDERING INFORMATION ........... 2 PIN DESCRIPTION .......... 3 ELECTRICAL CHARACTERISTICS ...... 29
ABSOLUTE MAXIMUMS ........... 29 DC ELECTRICAL CHARACTERISTICS ......... 29 AC ELECTRICAL CHARACTERISTICS ......... 29 AC ELECTRICAL CHARACTERISTICS (CONT.) ........... 31 1.0 Timing Diagrams ...... 36 Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L58 Device is operating in both the DS3 and Loop-Timing Modes ....... 36 Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L58 Device is operating in both the DS3 and Local-Timing Modes ............ 36 Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L58 Device is operating in both the DS3/Nibble and Looped-Timing Modes ..... 37 Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L58 Device is operating in the DS3/Nibble and Local-Timing Modes ........ 37 Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .......... 38 Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .......... 38 Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the rising edge of "TxLineClk" ............ 39 Figure 10. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the falling edge of "TxLineClk" ........... 39 Figure 11. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the rising edge of "RxLineClk" ............ 40 Figure 12. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the falling edge of "RxLineClk" ........... 40 Figure 13. Receive Payload Data Output Interface Timing ......... 41 Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ....... 41 Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ....... 42 Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) .......... 42 Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ..... 43 Figure 18. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ..... 43 Figure 19. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ............ 44 Figure 20. Microprocessor Interface Timing - Intel Type Write Burst Access Operation ............ 44 Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ........ 45 Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ......... 45 Figure 23. Microprocessor Interface Timing - Reset Pulse Width ........ 46 2.0 The Microprocessor Interface Block ....... 47
2.1 CHANNEL SELECTION WITHIN THE XRT72L58 DEVICE ......... 47
TABLE 1: THE RELATIONSHIP BETWEEN ADDRESS BITS A9, A10 AND A11 THE SELECTED CONFIGURATION REGISTER BANK ........... 47 Figure 24. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .......... 48
2.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .... 48
TABLE 2: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND MOTOROLA MODES .......... 49 TABLE 3: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTERFACE IS OPERATING IN THE INTEL MODE ........ 49
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