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Details, datasheet, quote on part number:XRT72L71
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| Part: | XRT72L71 |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) |
| Description: | Single-Chip, Single-channel Atm Unis For DS3 Atm |
| Company: | Exar Corporation |
| Datasheet: | Download XRT72L71 datasheet File size : 1185 kB |
| Request For quote: | Find where to buy XRT72L71
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Datasheet text preview:
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DECEMBER 2000
PRELIMINARY
XRT72L71
REV. P1.0.5
DS3 ATM UNI/CLEAR CHANNEL FRAMER
GENERAL DESCRIPTION
The XRT72L71 DS3 ATM User Network Interface (UNI)/Clear-Channel Framer is designed to function as either a DS3 ATM UNI or Clear channel framer. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-layers) interface for both the public and private networks at DS3 rates. For Clear-Channel framer applications, this device supports the transmission and reception of "user data" via the DS3 payload bits. The XRT72L71incorporates Receive, Transmit, Microprocessor Interface, Performance Monitor, Test and Diagnostic and Line Interface Unit Scan Drive sections. APP L ICATIONS · Private User Network Interfaces · ATM Switches · ATM Concentrators · DSLAM Equipment · DS3 Frame Relay Equipment
FEATURES · Compliant with UTOPIA Level 1 and 2 with 8 or 16 Bit Interface Specification and supports UTOPIA Bus speeds of up to 50 MHz · Contains on-chip 16 cell FIFO in both the Transmit (TxFIFO) and Receive Directions (RxFIFO) · Contains on-chip 54 byte Transmit OAM Cell buffer and a 108 byte Receive OAM cell buffer, for transmission, reception and processing of OAM cells. · Suppor ts PLCP or ATM Direct Mapping modes · Suppor ts M13 and C-Bit Parity Framing Formats · Suppor ts DS3 Clear Channel Framing Applications · Includes PRBS Generator and Receiver · Suppor ts Local, Remote-Line, Cell, and PLCP Loop-backs · Interfaces to 8 or 16 Bit wide Motorola and Intel µPs · Low power 3.3V, 5V input tolerant, CMOS · 160 pin PQFP Package · 3 and 4 Channel Version also Available
FIGURE 1. XRT72L71 SIMPLIFIED BLOCK DIAGRAM WITH SYSTEM INTERFACES
UTOPIA BUS
Level 1 or 2
TxUClav
XRT72L71 XRT73L00
Tx UTOPIA Interface Tx Cell Processor Tx PLCP Processor Tx DS3 Framer
ATM Layer Processor
16 Address 5
TxPOS TxNEG TCK DMO RLOS RLOL LLOOP RLOOP TAOS TxLEV EncoDis Req
TPDATA TNDATA TCK DMO RLOS RLOL LLB RLB TAOS TxLEV ENCODIS ReQDIS RPOS RNEG RCLK1
Tx
75 coax
Performance Monitor
LAPD Transceiver
FEAC Processor
Microprocessor Interface
LIU Interface Drive and Scan
DS3
44.736 MHz
Address 5 16 RxUClav
Rx UTOPIA Interface Rx Cell Processor Rx PLCP Processor Rx DS3 Framer
RxPOS RxNEG RxLineClk
75 coax
Rx
DS3/E3 LIU ATM Switch
25, 33 or 50 MHz D[15:0] D[7:0] A[8:0]
WR_RW 4 ALE_AS RD_DS RDY_DTCK
Intel/Motorola µP µ
Configuration, Control and Status Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRT72L71 DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
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PRELIMINARY
FIGURE 2. BLOCK DIAGRAM OF THE XRT72L71 DS3 UNI
A[8:0] WR_RW RD_DS CS ALE_AS Reset Int D[15:0] Width16 MOTO/Intel RDY_DTCK TxPOS TxNEG TxFrame TxOHClk TxLineClk TxAISEn TxFrameRef TxInClk TxOHIns TxOHFrame TxOH TxPOHFrame 8KRef StuffCtl TxOHInd/TxPFrame TxSerData/TxPOH TxPOHClk TxPOHIns TxCellTxed TxGFCClk TxGFCMSB TxGFC TxUClk TxUData[15:0] TxUPrty TxUSoC TxUEn TxUClav TxUAddr[4:0]
Test and Diagnostic Microprocessor Interface (Programmable Registers and Interrupt Block)
Performance Monitor
TDO TDI TestMode TCK TMS
Line Interface Drive and Scan
Receiver Transmitter FEAC Processor Transmit DS3 Framer Receive DS3 Framer
LAPD Transceiver
RxLineClk RxNEG RxPOS RLOS RxAIS RxOHClk RxOH RxSerClk RxLOS RxFrame RxOHFrame RxOOF
TAOS DMO RLOL TxLev RLOOP LLOOP Req RxRed EncoDis
Transmit PLCP Processor/ Clear Channel Transmit Serial Data Processor Transmit Cell Processor 54b OAM Buffer 16 cell FIFO
Receive PLCP Processor/ Clear Channel Receive Serial Data Processor Receive Cell Processor 2x54b OAM Buffer 16 cell FIFO
Transmit UTOPIA Interface
Receive UTOPIA Interface
RxPRed RxPOHFrame RxSerClk/RxPOHClk RxSerData/RxPOH RxOHInd/RxPFrame RxPLOF RxPOOF RxLCD RxCellRxed RxGFCClk RxGFCMSB RxGFC RxUClk RxUEn RxUPrty RxUData[15:0] RxUSoC RxUClav RxUAddr[4:0]
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PRELIMINARY
SYSTEM/FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION
The XRT72L71 DS3 ATM UNI/Framer IC can be configured to operate in either the "ATM UNI" or in the "Clear-Channel-Framer" Mode. A brief listing of the features and description for each of these operating modes is presented below. THE ATM UNI MODE OF OPERATION When the XRT72L71 UNI/Framer has been configured to operate in the "ATM UNI" Mode, it can functionally be subdivided into 6 different sections, as shown in Figure 2. · Receive Section · Transmit Section · Microprocessor Interface Section · Performance Monitor Section · Test and Diagnostic Section · Line Interface Unit Scan Drive Section The features of each of these functional sections are briefly outlined below. THE RECEIVE SECTION The purpose of the Receive Section of the XRT72L71 DS3 ATM UNI is to allow a local ATM Layer (or ATM Adaptation Layer) processor to receive ATM cell data from a remote piece of equipment via a public or leased DS3 transport medium. The Receive Section of the XRT72L71 DS3 UNI consists of the following functional blocks. · Receive DS3 Framer Block · Receive PLCP (Physical Layer Convergence Protocol) Processor Block · Receive Cell Processor Block · Receive UTOPIA Interface Block Each of these functional blocks, within the Receive Section of the UNI Framer will do the following: The Rx DS3 Framer Block · Capable of receiving data, from the LIU IC, in either the "Single-Rail" or "Dual-Rail" mode. · Capable of "sampling" the "inbound" DS3 data (at the "RxPOS" and "RxNEG" input pins) upon either the rising or falling edge of the "RxLineClk" signal. · The Receive DS3 Framer will synchronize to the incoming DS3 data stream and remove or process
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. P1.0.5
the DS3 Framing/Overhead Bits. This procedure will result in either extracting PLCP frame data or "Direct-Mapped" ATM Cell data, from the payload portion of the incoming DS3 data stream. · The Receive DS3 Framer can be used to receive FEAC (Far End Alarm & Control) messages via an on-chip FEAC Transceiver. · The Receive DS3 Framer includes an on-chip LAPD Receiver along with 88 bytes of on-chip RAM that can receive incoming path maintenance data link messages from the Remote Terminal Equipment. · Detects and generates interrupts upon "Detection of P and CP-bit Errors", "Change of State in LOS, AIS, OOF and FERF", "Receipt of New LAPD (PMDL) Message", "Validation and Removal of FEAC Message".
NOTE: The Receive DS3 Framer supports both M13 and Cbit Parity Frame Formats.
The Rx PLCP Processor Block · The Receive PLCP Processor will identify the frame boundary of each incoming PLCP frame, extract and process the overhead bytes of these PLCP frames (applies only if the UNI is operating in the PLCP Mode). The Receive PLCP Processor will also perform some error checking on the incoming PLCP frames. The Receive PLCP Processor will inform the Remote Terminal Equipment of the results of this error-checking by internally routing these results to the "Near-End" Transmit PLCP Processor, for transmission back out to the RemoteTerminal Equipment. The Rx Cell Processor Block · The Receive Cell Processor will perform the following functions: Cell Delineation HEC Byte Verification of incoming cells (optional) Cell-payload de-scrambling (optional) Idle cell detection and removal (optional) User and OAM Cell Filtering (optional) OAM Cell Processing (optional) · The UNI provides 108 bytes of on-chip RAM that allows for the reception and processing of selected OAM cells. · The Receive Cell Processor block will also verify the CRC-10 value within all received OAM cells, per ITU-T I.610.
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