|
Details, datasheet, quote on part number:XRT7300
| |
| Part: | XRT7300 |
| Category: | Communication => Network => SONET/SDH/ATM/DS3/PHYs/E3 (T3/E3) => Line Interfaces |
| Description: | DS3/E3/STS-1 Line Interface Unit |
| Company: | Exar Corporation |
| Datasheet: | Download XRT7300 datasheet File size : 620 kB |
| Request For quote: | Find where to buy XRT7300
|
| |
Datasheet text preview:
áç áç
JUNE 2001
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.0
GENERAL DESCRIPTION
The XRT7300 DS3/E3/STS-1 Line Interface Unit is designed to be used in DS3, E3 or SONET STS-1 applications and consists of a line transmitter and receiver integrated on a single chip. XRT7300 can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. In the transmit direction, the XRT7300 encodes input data to either B3ZS (for DS3/STS-1 applications) or HDB3 (for E3 applications) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction the XRT7300 performs equalization on incoming signals, performs Clock Recover y, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of line code violations. The XRT7300 also contains a 4-Wire Microprocessor Serial Interface for accessing the on-chip Command registers. FIGURE 1. BLOCK DIAGRAM OF THE XRT7300
E3 STS-1/DS3 Host/(HW)
FEATURES · Meets E3/DS3/STS-1 Jitter Tolerance Requirements · Full Loop-Back Capability · Transmit and Receive Power Down Modes · Full Redundancy Support · Contains a 4-Wire Microprocessor Serial Interface · Uses Minimum External components · Requires Single +5V Power Supply · -40°C to +85°C Operating Temperature Range · Available in a 44 pin TQFP package APPLICATIONS · Interfaces to E3, DS3 or SONET STS-1 Networks · CSU/DSU Equipment · PCM Test Equipment · Fiber Optic Terminals · Multiplexers
NOTE: This Device is Protected by US Patent # 6,157,270
RLOL EXCLK
ICT
RCLK2INV
RTIP RRING REQDIS
AGC/ Equalizer Peak Detector
Slicer
Clock Recovery Data Recovery
Invert
RCLK1 LCV/(RCLK2)
LOSTHR SDI SDO/(LCV) SClk CS REGRESET TTIP Pulse Shaping TRING MTIP MRING DMO Tx Control Serial Processor Interface
LOS Detector
HDB3/ B3ZS Decoder
RPOS RNEG DECODIS RLOS LLB RLB ENCODIS TAOS TPDATA TNDATA
Loop MUX
HDB3/ B3ZS Encoder
Transmit Logic Duty Cycle Adjust
TClk TXLEV TXOFF
Device Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com
XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.0
áç
ORDERING INFORMATION
PART NUMBER XRT7300IV PACKAGE TYPE 44 Pin TQFP (10mm x 10mm) OPERATING TEMPERATURE RANGE -40°C to +85°C
FIGURE 2. PIN OUT OF THE XRT7300 IN THE 44 PIN TQFP
TNDATA TPDATA
MRING
TXOFF 35
TRING
TCLK
MTIP
GND
TTIP
VDD
44
43
42
41
40
39
38
37
36
34
TxLEV TAOS VDD DMO GND GND GND RTIP RRING VDD REGRESET/ RCLK2INV
1 2 3 4 5 6 7 8 9 10 11
I CT 33 32 31 30 29 28 27 26 25 24 23
RPOS RNEG RCLK1 LCV/(RCLK2) VDD GND EXCLK VDD GND RLOS RLOL
XRT7300 (Top View)
12 REQDIS
13 LOSTHR
14 LLB
15 RLB
16 STS1/DS3
17 E3
18 HOST/HW
19 SDI/(LOSMUTEN)
20 SDO/(LCV)
21 SCLK/(ENCODIS)
22 CS/(DECODIS)
2
áç áç
E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7300
REV. 1.1.0
TABLE OF CONTENTS General description .. 1
FEATURES ....... 1 APPLICATIONS ......... 1 Figure 1.Block Diagram of the XRT7300... 1
Ordering Information ......... 2
Figure 2.Pin Out of the XRT7300 in the 44 Pin TQFP....... 2
TABLE OF CONTENTS ......... I Pin Description .......... 3 Electrical Characteristics ...... 10
DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED) ...... 10 AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED) ...... 10 Figure 3.Timing Diagram of the Transmit Terminal Input Interface ...... ... 11 Figure 4.Timing Diagram of the Receive Terminal Output Interface ....... 11 AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED) ......... 12 AC ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 5.0V + 5%, UNLESS OTHERWISE SPECIFIED) ......... 13
ABSOLUTE MAXIMUM RATINGS .... 14
Figure 5.Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates ..... 15 Figure 6.ITU-T G.703 Transmit Output Pulse Template for E3 Applications.... 15 Figure 7.Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications....... 16 Figure 8.Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ..... 16 MICROPROCESSOR SERIAL INTERFACE TIMING (SEE FIGURE 9) ........ 17 Figure 9.Timing Diagram for the Microprocessor Serial Interface ........... 17
System Description ......... 18
THE TRANSMIT SECTION ..... 18 THE RECEIVE SECTION ....... 18 THE MICROPROCESSOR SERIAL INTERFACE ... 18 Table 1:Role of Microprocessor Serial Interface pins when the XRT7300 is operating in the Hardware Mode 18 1.0 SELECTING THE DATA RATE ...... 19
Table 2:Selecting the Data Rate for the XRT7300 via the E3 and STS-1/DS3 input pins (Hardware Mode)... 19 COMMAND REGISTER CR4 (ADDRESS = 0X04) .......... 19 Table 3:Selecting the Data Rate for the XRT7300 Via the STS-1/DS3 and the E3 Bit-fields Within Command Register CR4 (HOST Mode)....... 19
2.0 THE TRANSMIT SECTION .... 20 2.1 THE TRANSMIT LOGIC BLOCK ........ 20 Figure 10.The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Terminal Equipment to the Transmit Section of the XRT7300 ....... 20 Figure 11.How the XRT7300 Samples the Data on the TPDATA and TNDATA Input Pins..... 20 Accepting Single-Rail Data from the Terminal Equipment ......... 21 COMMAND REGISTER CR1 (ADDRESS = 0X01) .......... 21 Figure 12.The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting Single-Rail Data From the Terminal Equipment......... 21
I
|
|
