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The is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion a 1-of-24 decoder using just three AC/ACT138 devices a 1-of-32 decoder using four AC/ACT138 devices and one inverter.Features
s ICC reduced 50% s Demultiplexing capability s Multiple input enable for easy expansion s Active LOW mutually exclusive outputs s Outputs source/sink s ACT138 has TTL-compatible inputs
Order Number 74ACT138SJ 74ACT138PC Package Number M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.Pin Names E3 O0O7 Description Address Inputs Enable Inputs Enable Input Outputs
The AC/ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs A1, A2) and, when enabled, provides eight mutually exclusive activeLOW outputs (O0O7). The AC/ACT138 features three Enable inputs, two active-LOW (E1, E2) and one activeHIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device 1-of-32 (5 lines to 32 lines) decoder with just four AC/ACT138 devices and one inverter (see Figure 1). The AC/ACT138 can be used an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active-HIGH or active-LOW state.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from to 2.0V VCC 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) VOL Maximum LOW Level Output Voltage IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current = +25°C Typ to +85°C Guaranteed Limits VIN = VIL or VIH VIN = VIL or VIH µA V IOL 24 mA IOL mA 0 IOL 24 mA (Note VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT µA V IOH -12 mA IOH -24 mA IOH -24 mA (Note 2) V IOUT µA V VOUT 0.1V or VCC 0.1V V Units Conditions VOUT 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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