The is a high-speed, dual 1-of-4 decoder/ demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutuallyexclusive active-LOW outputs. Each decoder has an active-LOW Enable input which can be used as a data input for a 4-output demultiplexer. Each half of the AC/ ACT139 can be used as a function generator providing all four minterms of two variables.
s ICC reduced 50% s Multifunction capability s Two completely independent 1-of-4 decoders s Active LOW mutually exclusive outputs s Outputs source/sink s ACT139 has TTL-compatible inputs
Order Number 74ACT139MTC 74ACT139PC Package Number MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pin Names E O0O3 Description Address Inputs Enable Inputs Outputs
The is a high-speed dual 1-of-4 decoder/ demultiplexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A0A1) and provides four mutually exclusive active-LOW outputs (O0O3). Each decoder has an active-LOW enable (E). When E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4-output demultiplexer application. Each half of the AC/ACT139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure 1, and thereby reducing the number of packages required in a logic network.
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP -0.5V to VCC -0.5V to VCC to +7.0V
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from to 2.0V VCC 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) VOL Maximum LOW Level Output Voltage IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current = +25°C Typ to +85°C Guaranteed Limits VIN = VIL or VIH VIN = VIL or VIH µA V IOL 12 mA IOL 24 mA IOL 24 mA (Note VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT µA V IOH -12 mA IOH -24 mA IOH -24 mA (Note 2) V IOUT µA V VOUT 0.1V or VCC 0.1V V Units Conditions VOUT 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.