Details, datasheet, quote on part number: 74AC163
Part74AC163
CategoryLogic => Counters => CMOS/BiCMOS->AC/ACT Family
TitleCMOS/BiCMOS->AC/ACT Family
DescriptionSynchronous Presettable Binary Counter
CompanyFairchild Semiconductor
DatasheetDownload 74AC163 datasheet
Cross ref.Similar parts: 74AC163B, 74AC163M, 74AC163MTR, 74AC163TTR, CD54AC163F, CD54AC163F/3A, CD54AC163FX, CD74AC163E, CD74AC163EX, CD74AC163M
Quote
Find where to buy
 
  

 

Features, Applications

The AC/ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.

Features

s ICC reduced 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink s ACT163 has TTL-compatible inputs

Order Number 74ACT163MTC 74ACT163PC Package Number MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Pin Names CEP CET Q0­Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output

The AC/ACT163 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: synchronous reset, parallel load, count-up and hold. Four control inputs--Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)--determine the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT163 uses D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Action on the Rising Clock Edge ( Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable = CEP CET Q2 Q3 CET

Reset (Clear) Load (Pn Qn) Count (Increment) No Change (Hold) No Change (Hold)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.


 

Related products with the same datasheet
74AC163CW
74AC163MTC
74AC163MTCX
74AC163PC
74AC163SC
74AC163SCX
74AC163SJ
74AC163SJX
Some Part number from the same manufacture Fairchild Semiconductor
74AC163CW Synchronous Presettable Binary Counter
74AC169 4-Stage Synchronous Bidirectional Counter
74AC174 Hex D Flip-flop With Master Reset
74AC175 Quad D-type Flip-flop
74AC191 Up/down Counter With Preset And Ripple Clock
74AC20 Dual 4-Input NAND Gate
74AC240 Octal Buffer/line Driver With 3-STATE Outputs
74AC241
74AC244
74AC245 Octal Bidirectional Transceiver With 3-STATE Inputs/ Outputs
74AC251 8-Input Multiplexer With 3-STATE Output
74AC253 Dual 4-Input Multiplexer With 3-STATE Outputs
74AC257 Quad 2-Input Multiplexer With 3-STATE Outputs
74AC273 Octal D-type Flip-flop
74AC27374ACT273
74AC273MTC
74AC280 9-Bit Parity Generator/checker
74AC299 8-Input Universal Shift/storage Register With Common I/o Pins
74AC32 Quad 2-Input OR GATE
Same catergory

5962-8550601VRA : Standard Transceivers. ti SN54HCT245, Octal Bus Transceivers With 3-State Outputs.

74HC3G14 : 74HC3G14; 74HCT3G14; Triple Inverting Schmitt-trigger;; Package: SOT505-2 (TSSOP8).

CD4510BMS : Synchronous Counters-> CMOS/BiCMOS->HC/HCT Family. Radiation Hardened CMOS Presettable Up/down Counters.

CD74HC283E : Adders. ti CD74HC283, High Speed CMOS Logic 4-Bit Binary Full Adder With Fast Carry.

CD74HC365 : CMOS/BiCMOS->HC/HCT Family. High Speed CMOS Logic Hex Buffer/line Driver, Three-state Non-inverting And Inverting.

HEF4023BGATES : CMOS/BiCMOS->4000 Family. Triple 3-input NAND Gate. For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family s HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC Product File under Integrated Circuits, IC04 January 1995 The HEF4023B provides the positive triple 3-input NAND function. The outputs are fully buffered for highest noise immunity and pattern.

MC74LCX08SD : Low-voltage CMOS Quad 2-input And Gate. The is a high performance, quad 2­input AND gate operating from to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI of 5.5V allows MC74LCX08 inputs to be safely driven from 5V devices. Current drive capability 24mA at the outputs.

MC74LVXU04D : Hex Inverter , Package: Soic, Pins=14. The is an advanced high speed CMOS unbuffered hex inverter. The inputs tolerate voltages 7 V, allowing the interface 5 V systems 3 V systems. High Speed: tPD 4.1 ns (Typ) at VCC 3.3 V Low Power Dissipation: ICC 2 µA (Max) = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP 0.5 V (Max) Pin and Function Compatible.

MC74VHC1G14 : CMOS/BiCMOS->HC/HCT Family. Schmitt-trigger Inverter. The is a single gate CMOS Schmitt­trigger inverter fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The MC74VHC1G14 input structure provides protection when voltages 7.0 V are applied, regardless of the supply voltage. This.

MM74C00 : CMOS/BiCMOS->4000 Family. Quad 2-input NAND Gate. MM74C00 Quad 2-Input NAND Gate MM74C02 Quad 2-Input NOR Gate MM74C04 Hex Inverter MM74C10 Triple 3-Input NAND Gate MM74C20 Dual 4-Input NAND Gate These logic gates employ complementary MOS (CMOS) to achieve wide power supply operating range low power consumption high noise immunity and symmetric controlled rise and fall times With such as this the 54C 74C logic.

SN54HC164FK : 8-bit Parallel-out Serial Shift Registers. AND-Gated (Enable / Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input.

SN54LS393FK : Dual 4-bit Decade And Binary Counters. PRODUCTION DATA information is current as of publication date. Products conform to s per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. .

SN55138FK : Quadruple Bus Transceivers. Single 5-V Supply High-Input-Impedance, High-Threshold Receivers Common Driver Strobe TTL-Compatible Driver and Strobe Inputs With Clamp Diodes High-Speed Operation 100-mA Open-Collector Driver Outputs Four Independent Channels TTL-Compatible Receiver Output The SN55138 and SN75138 quadruple bus transceivers are designed for two-way data communication.

SN74BCT29846 : CMOS/BiCMOS->ABT/BCT Family. 8-bit Bus-interface D-type Latch With 3-state Output.

SN74S299 : Bipolar->TTL Family. 8-bit Universal Shift/storage Register With 3-state Outputs.

SY10/100E164 : . s 850ps Data Input to Output s Extended 100E VEE range ­5.5V s Differential output s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pull-down resistors s Fully compatible with Motorola MC10E/100E164 s Available in 28-pin PLCC package The SY10/100E164 are 16:1 multiplexers with a differential output. The select inputs.

SY89250V : Enhanced Differential Receiver.

A2F200M3C-PQG208 : FPGA, 4608 CLBS, 200000 GATES, PQFP208. s: System Gates: 200000 ; Logic Cells / Logic Blocks: 4608 ; Package Type: QFP, Other, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 ; Logic Family: CMOS ; Pins: 208 ; Operating Temperature: 0 to 85 C (32 to 185 F) ; Supply Voltage: 1.5V.

A3P030-1QN48II : FPGA, 768 CLBS, 30000 GATES, 350 MHz, QCC48. s: System Gates: 30000 ; Logic Cells / Logic Blocks: 768 ; Package Type: Other, 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, QFN-48 ; Logic Family: CMOS ; Pins: 48 ; Internal Frequency: 350 MHz ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Supply Voltage: 1.5V.

A3P1000-1FGG144C : FPGA, 24576 CLBS, 1000000 GATES, 350 MHz, PBGA144. s: System Gates: 1.00E6 ; Logic Cells / Logic Blocks: 24576 ; Package Type: Other, 1 MM PITCH, GREEN, FBGA-144 ; Logic Family: CMOS ; Pins: 144 ; Internal Frequency: 350 MHz ; Operating Temperature: 0 to 70 C (32 to 158 F) ; Supply Voltage: 1.5V.

 
0-C     D-L     M-R     S-Z