Details, datasheet, quote on part number: 74AC169CW
CategoryLogic => Counters => CMOS/BiCMOS->AC/ACT Family
Description4-Stage Synchronous Bidirectional Counter
CompanyFairchild Semiconductor
DatasheetDownload 74AC169CW datasheet


Features, Applications

The AC169 is fully synchronous 4-stage up/down counter. The a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.


s ICC reduced 50% s Synchronous counting and loading s Built-In lookahead carry capability s Presettable for programmable operation s Outputs source/sink 24 mA

Order Number 74AC169MTC 74AC169PC Package Number MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Pin Names CEP CET P0P3 PE U/D Q0Q3 TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Parallel Data Inputs Parallel Enable Input Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output

The AC169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the AC169 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use as a clock signal is not recommended (see logic equations below). 1. Count Enable = CEPCET PE 2. Up: 2Q3(Up)CET 3. Down: Q0 Q1Q2Q3(Down)CET

Action on Rising PE CEP CET U/D Clock Edge Load (Pn to Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold)

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP -0.5V to VCC -0.5V to VCC to +7.0V

Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 70% of VCC 5.5V 125 mV/ns 0V to VCC 0V to VCC to +85C

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) VOL Maximum LOW Level Output Voltage IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current = +25C Typ to +85C Guaranteed Limits VIN = VIL or VIH VIN = VIL or VIH A V IOL 12 mA IOL 24 mA IOL 24 mA (Note VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT A V IOH -12 mA IOH -24 mA IOH -24 mA (Note 2) V IOUT A V VOUT 0.1V or VCC 0.1V V VOUT 0.1V or VCC - 0.1V Units Conditions

Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.


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