Details, datasheet, quote on part number: 74AC174PC
DescriptionHex D Flip-flop With Master Reset
CompanyFairchild Semiconductor
DatasheetDownload 74AC174PC datasheet
Cross ref.Similar parts: 74AC174B, CD54AC174F, CD54AC174F/3A, CD54AC174F3A, CD74AC174E, CD74AC174EX, HD74AC174P, M38510/75307BEA
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Features, Applications

The is a high-speed hex D-type flip-flop. The device is used primarily a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops.


Order Number 74ACT174MTC 74ACT174PC Package Number MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Pin Names MR Q0Q5 Description Data Inputs Clock Pulse Input Master Reset Input Outputs

The AC/ACT174 consists of six edge-triggered D-type flipflops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flipflop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Supply Voltage (VCC) DC Input Diode Current (IIK) VI = VCC 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) V = VCC 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C

Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 70% of VCC 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from to 2.0V VCC 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) VOL Maximum LOW Level Output Voltage IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current = +25C Typ to +85C Guaranteed Limits VIN = VIL or VIH VIN = VIL or VIH A V IOL 12 mA IOL 24 mA IOL 24 mA (Note VI = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT A V IOH -12 mA IOH -24 mA IOH -24 mA (Note 2) V IOUT A V VOUT 0.1V or VCC 0.1V V Units Conditions VOUT 0.1V or VCC - 0.1V

Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.


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