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Details, datasheet, quote on part number:74AC648
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| Part: | 74AC648 |
| Category: | Logic => Bus Interface => Bus Oriented Circuits |
| Description: | Octal Bus Transceiver/register With 3-STATE Outputs |
| Company: | Fairchild Semiconductor |
| Datasheet: | Download 74AC648 datasheet File size : 75 kB |
| Request For quote: | Find where to buy 74AC648
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Datasheet text preview:
74AC648 Octal Transceiver/Register with 3-STATE Outputs
November 1988 Revised August 2000
74AC648 Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4.
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Inverted data to output
Ordering Code:
Order Number 74AC648SC 74AC648SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names A0A7 B0 B7 CPAB, CPBA SAB, SBA DIR, G Description Data Register A Inputs, Data Register A 3-STATE Outputs Data Register B Inputs, Data Register B 3-STATE Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Inputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010133
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74AC648
Function Table
Inputs G H H H L L L L L L L L DI R X X X H H H H L L L L CPAB CPBA H or L H or L S AB X X X L L H H X X X X SBA X X X X X X X L L H H Output Input Input Input Input Data I/O (Note 1) A0A7 B0 B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An --Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Function
X
X X X X
X
H or L
X X X X
X
H or L
H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition
X
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Real Time Transfer A-Bus to B-Bus
Real Time Transfer B-Bus to A-Bus
FIGURE 1. Storage from Bus to Register
FIGURE 2. Transfer from Register to Bus
FIGURE 3.
FIGURE 4.
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74AC648
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC648
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V ± 50 mA ± 50 mA -65°C to +150°C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V 2.0V to 6.0V 0V to VCC 0V to VCC
-40°C to +85°C
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage V CC (V) 3.0 4.5 5.5 3 .0 4.5 5.5 3.0 4 .5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3 .0 4 .5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) IOZT Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 ± 0.6 ±6.0 µA 5.5 5.5 5.5 5.5 8 .0 0.002 0.001 0.001 TA = +25°C Typ 1 .5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3 .15 3 .85 0.9 1 .35 1 .65 2.9 4.4 5 .4 2 .56 3 .86 4 .86 0 .1 0 .1 0.1 0 .36 0 .36 0 .36 ±0.1 TA = -40°C to +85°C Guaranteed Limits 2 .1 3 .15 3 .85 0 .9 1 .35 1 .65 2 .9 4 .4 5.4 VIN = VIL or VIH 2 .46 3 .76 4 .76 0.1 0.1 0 .1 VIN = VIL or VIH 0 .44 0 .44 0 .44 ± 1.0 75 -75 80.0 µA mA mA µA V IOL= 12 mA IOL = 24 mA IOL = 24 mA (Note 3) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions VOUT = 0.1V
V
or VCC - 0.1V VOUT = 0.1V
V
or VCC - 0.1V
V
IOUT = -50 µA
IOH= -12 mA V IOH= -24 mA IOH= -24 mA (Note 3) V IOUT = 50 µA
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74AC648
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPLH tPHL tPLH Parameter Propagation Delay Clock to Bus Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An or Bn (with An or Bn HIGH or LOW) tPHL Propagation Delay SBA or SAB to An or B n (with An or Bn HIGH or LOW) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Enable Time G to An or Bn Enable Time G to An or Bn Disable Time G to An or Bn Disable Time G to An or Bn Enable Time DIR to An or Bn Enable Time DIR to An or Bn Disable Time DIR to An or Bn Disable Time DIR to An or Bn 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1.5 1 .5 1.5 1 .5 1.5 1 .5 1.5 1 .5 1.5 1 .5 1.5 1 .5 1.5 1 .5 1.5 1 .5 6.5 5.0 7.0 5.0 7.5 6.0 7.0 5.5 6.0 4.5 6.5 4.5 7.0 5.5 7.0 5.0 11.0 8 .0 11.0 8 .0 12.0 10.0 11.5 9 .0 12.5 9 .5 13.0 9 .0 11.5 9 .0 13.5 9 .5 1.0 1.0 1.0 1.0 1.0 1 .0 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.5 1.0 11.5 9.0 12.5 9.0 13.0 11.0 12.5 10.0 14.0 10.5 14.5 10.5 13.5 10.0 15.0 10.0 ns ns ns ns ns ns ns ns 3.3 5.0 1.5 1 .5 7.5 5.5 12.5 9 .5 1.5 1.5 14.0 10.5 ns (V) (Note 6) 3.3 5 .0 3.3 5 .0 3.3 5 .0 3.3 5 .0 3.3 5.0 Min 1 .5 1.5 1.5 1.5 1 .5 1.5 1 .5 1.5 1.5 1 .5 TA = +25°C CL = 50 pF Typ 10.0 7.0 8.5 6.0 6.0 4.0 5.5 3.5 7.5 5.5 M ax 15.5 11.0 13.5 10.5 10.0 7.0 9 .0 7.5 12.5 9 .0 TA = -40°C to +85°C CL = 50 pF M in 1 .5 1.5 1.5 1 .5 1 .5 1 .0 1.5 1 .0 1.5 1.5 Max 17.0 12.0 14.5 11.5 11.0 7.5 10.0 8.0 14.0 10.0 ns ns ns ns ns Units
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
V CC Symbol Parameter (V) (Note 7) tS tH tW Setup Time, HIGH or LOW, Bus to Clock Hold Time, HIGH or LOW, Bus to Clock Clock Pulse Width HIGH or LOW 3.3 5.0 3 .3 5.0 3 .3 5 .0 TA = +25°C CL = 50 pF Typ 2 .0 1 .5 -1.5 -0.5 2.0 2.0 3.0 2.0 0 1 .0 3 .5 3 .0 TA = -40°C to +85°C CL = 50 pF Guaranteed Minimum 3.5 2.0 0 1.0 4.0 3.0 ns ns ns Units
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V; Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol CIN CPD CI/O Input Capacitance Power Dissipation Capacitance Input/Output Capacitance Parameter Typ 4.5 65.0 15.0 Units pF pF pF Conditions VCC = OPEN VCC = 5.0V VCC = 5.0V
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