|
|
Part: 74ACT16240MTD
Category:
Description: 16-Bit Inverting Buffer/line Driver With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74ACT16240MTD datasheet File size : 232 kB
Request For quote: Find where to buy 74ACT16240MTD
Datasheet text preview:
74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
August 1999 Revised October 1999
74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
Features
s Separate control logic for each byte s 16-bit version of the ACT240 s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:
Order Number 74ACT16240SSC 74ACT16240MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names O En I0I15 O0O15 Description Output Enable Inputs (Active LOW) Inputs Outputs
FACTTM is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500293
www.fairchildsemi.com
74ACT16240
Truth Tables
Inputs OE1 L L H I0I3 L H X Outputs O0O3 H L Z OE2 L L H Inputs I4I7 L H X Outputs O4O7 H L Z
Inputs OE3 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Outputs I8I11 L H X O8O11 H L Z OE4 L L H
Inputs I12I15 L H X
Outputs O12O15 H L Z
Functional Description
The ACT16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Logic Diagram
www.fairchildsemi.com
2
74ACT16240
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature ± 50 mA +140°C -65°C to +150°C -20 mA +20 mA -0.5V to VCC + 0.5V ± 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5.5 5.5 0 .6 8 .0 0.001 0.001 TA = +25°C Typ 1 .5 1.5 1.5 1.5 4 .49 5.49 2.0 2.0 0.8 0.8 4 .4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.5 ± 0.1 TA = -40°C to +85°C Guaranteed Limits 2 .0 2.0 0.8 0.8 4.4 5 .4 3 .76 4 .76 0.1 0 .1 0 .44 0 .44 ±5.0 ± 1.0 1.5 80.0 75 -75 µA µA mA µA mA mA V V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Units Conditions
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
3
www.fairchildsemi.com
74ACT16240
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = +25°C CL = 50 pF Min 2.7 3.0 2.5 2.7 2.3 2.0 Typ 4.8 5.1 4.5 4.7 5.0 4.6 Max 7.3 7.3 7.4 7.5 7.9 7.4
TA = -40°C to +85°C CL = 50 pF M in 2 .7 3 .0 2 .5 2 .7 2 .3 2 .0 Max 7.8 7.8 7.9 8.0 8.2 7.9 ns ns ns Units
Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time
(V) (Note 4) 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
www.fairchildsemi.com
4
74ACT16240
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
5
www.fairchildsemi.com
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
