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Details, datasheet, quote on part number:74ACT533SCX
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Datasheet text preview:
74ACT533 Octal Transparent Latch with 3-STATE Outputs
August 1999 Revised October 1999
74ACT533 Octal Transparent Latch with 3-STATE Outputs
General Description
The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Features
s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Inverted version of the ACT373 s TTL-compatible inputs
Ordering Code:
Order Number 74ACT533SC 74ACT533MTC 74ACT533PC Package Number M20B MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0D7 LE OE O0O7 Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs
FACTTM is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500311
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74ACT533
Functional Description
The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
Inputs LE X H H L OE H L L L Dn X L H X Outputs On Z H L O0
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT533
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = - 0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = - 0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latchup Source or Sink Current Junction Temperature (TJ) PDIP 140°C ± 300 mA ± 50 mA - 65°C to + 150°C ± 50 mA - 20 mA + 20 mA - 0.5V to VCC + 0.5V - 20 mA + 20 mA -0.5V to VCC + 0.5V - 0.5V to + 7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate V/t VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns 4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD IC C Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.1 ±0.25 TA = -40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±1.0 ±2.5 1.5 75 -75 40.0 µA µA mA mA mA µA V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = V CC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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74ACT533
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 4) tPHL tPLH tPHL tPLH tPZL, tPZH tPHZ, tPLZ Propagation Delay Dn to On Propagation Delay LE to On Output Enable Time Output Disable Time 5.0 5.0 5.0 5.0 Min 2.0 2.5 2.0 1.0 TA = + 25°C CL = 50 pF Typ 6.0 7.0 7.0 8.0 M ax 8.0 9.0 9.0 10.0 TA = - 40°C to + 85°C CL = 50 pF Min 2.0 2.5 2.0 1.0 Max 8.5 9.5 9.5 10.5 ns ns ns ns Units
Note 4: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
VCC Symbol Parameter (V) (Note 5) tS tH tW Setup Time, HIGH or LOW Dn to LE Hold Time, HIGH or LOW Dn to LE LE Pulse Width, HIGH
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = + 25°C CL = 50 pF Typ 0 0 2.0
TA = - 40°C to + 85°C CL = 50 pF Guaranteed Minimum 3.0 1.5 4.0 3.0 1.5 4.0 ns ns ns Units
5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 40 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74ACT533
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300" Wide Body Package Number M20B
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