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Details, datasheet, quote on part number:74ACT541
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| Part: | 74ACT541 |
| Category: | Logic => Line Driver/Receivers => CMOS/BiCMOS->AC/ACT Family |
| Description: | Octal Buffer/line Driver With 3-STATE Outputs |
| Company: | Fairchild Semiconductor |
| Datasheet: | Download 74ACT541 datasheet File size : 81 kB |
| Request For quote: | Find where to buy 74ACT541
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Datasheet text preview:
74AC541 · 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988 Revised October 1999
74AC541 · 74ACT541 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74AC541 and 74ACT541 are octal buffer/line drivers designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. These devices are similar in function to the 74AC244 and 74ACTC244 while providing flow-through architecture (inputs on opposite side from outputs). This pinout arrangement makes these devices especially useful as an output port for microprocessors, allowing ease of layout and greater PC board density.
Features
s ICC and IOZ reduced by 50% s 3-STATE outputs s Inputs and outputs opposite side of package, allowing easier interface to microprocessors s Output source/sink 24 mA s 74AC541 is a non-inverting option of the 74AC540 s 74ACT541 has TTL-compatible inputs
Ordering Code:
Order Number 74AC541SC 74AC541SJ 74AC541MTC 74AC541PC 74ACT541SC 74ACT541MTC 74ACT541PC Package Number M20B M20D MTC20 N20A M20B MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Truth Table
Inputs OE1 L H X L
H = HIGH Voltage Level X = Immaterial FACTTM is a trademark of Fairchild Semiconductor Corporation.
OE2 L X H L
I H X X L
Outputs H Z Z L
Z = High Impedance
L = LOW Voltage Level
© 1999 Fairchild Semiconductor Corporation
DS009967
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74AC541 · 74ACT541
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C ± 50 mA -65°C to +150°C ± 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC: VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V ACT:VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C 125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Leakage Current IOLD IOHD Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5 .5 4.0 ±0.25 ±2.5 75 -75 40.0 µA mA mA µA 5.5 0.002 0.001 0.001 TA = +25°C Typ 1 .5 2.25 2.75 1 .5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2 .9 4 .4 5 .4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ± 0.1 TA = -40°C to +85°C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 ± 1.0 µA V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = V CC, GND VI (OE) = V IL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 µA V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 2) V IOUT = -50 µA V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
ICC (Note 4) Maximum Quiescent Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC541 · 74ACT541
AC Electrical Characteristics for AC
V CC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data to Output Propagation Delay Data to Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (V) (Note 5) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V
TA = +25°C CL = 50 pF Min 2.0 1.5 2.0 1.5 3.0 2.0 2.5 1.5 3.5 2.0 2.5 2.0 Typ 5.5 4.0 5.5 4.0 8.0 6.0 7.0 5.5 9.0 7.0 6.5 5.5 Max 8.0 6.0 8.0 6.0 11.5 8.5 10.0 7.5 12.5 9.5 9.5 7.5
TA = -40°C to +85°C CL = 50 pF Min 1.5 1.0 1.5 1.0 3.0 1.5 2.5 1.0 2.5 1.0 2.0 1.0 Max 9.0 6.5 8.5 6.5 12.5 9.5 11.5 8.5 14.0 10.5 10.5 8.5 ns ns ns ns ns ns Units
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 3.0 4.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 4.5 5.5 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current 0 .002 0 .001 TA = +25°C Typ 1 .5 1 .5 1 .5 1 .5 2 .99 4 .49 2.0 2.0 0.8 0.8 2 .9 4 .4 3.86 4.86 0.1 0.1 0.36 0.36 TA = -40°C to +85°C Guaranteed Limits 2 .0 2 .0 0 .8 0 .8 2.9 4.4 3.76 4.76 0 .1 0 .1 0.44 0.44 V V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VIL or VIH IOH = -24 mA IOH = -24 mA (Note 6) V IOUT = 50 µA VIN = VIL or VIH IOH = 24 mA IOH = 24 mA (Note 6) 5.5 5.5 5.5 5.5 5.5 5.5 4 .0 0 .6 ± 0.1 ±0.25 ± 1.0 ±2.5 1.5 75 -75 40.0 µA µA mA mA mA µA VI = V CC, GND VI = V IL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
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74AC541 · 74ACT541
AC Electrical Characteristics for ACT
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
TA = +25°C CL = 50 pF Min 2.0 2.0 2.0 2.0 1.5 1.5 Typ 4 .5 5 .5 5 .0 6 .5 5 .5 5 .5 Max 7 .0 7.0 9 .0 9 .0 7 .5 7 .5
TA = -40°C to +85°C CL = 50 pF Min 2.0 2.0 2.0 2.0 1.5 1.5 Max 7 .5 7.5 9 .5 9 .5 8 .0 8 .0 ns ns ns Units
Parameter Propagation Delay Data to Output Output Enable Time
(V) (Note 8) 5.0
5.0 Output Disable Time 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance for AC Power Dissipation Capacitance for ACT Typ 4 .5 30.0 70.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC541 · 74ACT541
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
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