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Details, datasheet, quote on part number:74ACTQ16373CW
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Datasheet text preview:
74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
June 1991 Revised April 2001
74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. The ACTQ16373 utilizes Fairchild's Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ373 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number 74ACTQ16373SSC 74ACTQ16373MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn LEn I0I15 O0O15 Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS010934
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74ACTQ16373
Functional Description
The ACTQ16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8I15 X L H X I0I7 X L H X Outputs O0O7 Z L H (Previous) Outputs O8O15 Z L H (Previous)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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74ACTQ16373
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature
-0.5V to +7.0V -20 mA +20 mA -20 mA +20 mA -0.5V to VCC + 0.5V +50 mA +50 mA +140 °C -65°C to+150°C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC
-40°C to +85°C
125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level 5.0 5.0 5.0 5.0 5.0 5.0 0.5 -0.5 0.8 - 1.0 5.5 5.5 5.5 5.5 5.5 0.6 8 .0 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5 .4 3.86 4.86 0.1 0.1 0.36 0.36 ± 0.5 ± 0.1 TA = -40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ± 5.0 ± 1.0 1.5 80.0 75 -75 µA µA mA µA mA mA V V V V V V V V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figures 1, 2 (Note 5)(Note 6) Figures 1, 2 (Note 5)(Note 6) Figures 1, 2 (Note 4)(Note 6) VOH - 1.0 VOH - 1.8 1.7 1.2 2.0 0.8 Figures 1, 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7) Units Conditions
VOH + 1.0 VOH + 1.5
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package Note 5: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH. Note 7: Max number of data inputs (n) switching, (n - 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD)
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74ACTQ16373
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Delay Output Disable Delay (V) (Note 8) 5.0 5.0 5.0 5.0 Min 3.1 2.6 3.1 2.8 2.5 2.7 2.1 2 .0 TA = +25°C CL = 50 pF Typ 5.3 4.6 5.4 4.9 4.7 4.8 5.1 4.5 Max 7.9 7.3 7.9 7.3 7.4 7.5 7.9 7 .4 TA = -40°C to +85°C CL = 50 pF Min 3.1 2 .6 3 .2 2 .8 2 .5 2 .7 2 .1 2.0 Max 8.4 7.8 8.4 7.8 7.9 8.0 8.2 7.9 ns ns ns ns Units
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
Extended AC Electrical Characteristics
TA = -40°C to +85°C VCC Symbol Parameter (V) (Note 9) Min tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 14) tOSLH (Note 14) tOST (Note 14) Propagation Delay Data to Output Propagation Delay Latch Enable to Output Output Enable Time Output Disable Time Pin-to-Pin Skew HL Data to Output Pin-to-Pin Skew LH Data to Output Pin-to-Pin Skew LH/HL Data to Output 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 4.7 4.6 4.6 4.1 3.5 3.6 3.4 3 .1 CL = 50 pF 16 Outputs Switching (Note 10) Max 12.7 10.6 13.3 10.4 10.4 10.9 8 .5 8 .1 1.3 2.1 4.0 Min 6.6 6.4 6.3 5.8 (Note 12) (Note 13) M ax 15.7 14.5 15.3 13.6 ns ns ns ns ns ns ns TA = -40°C to +85°C CL = 250 pF (Note 11) Units
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 13: The Output Disable Time is dominated by the RC Network (500, 250 pF) on the output and has been excluded from the datasheet. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST).
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74ACTQ16373
AC Operating Requirements
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW, Input to Clock Hold Time, HIGH or LOW Input to Clock CS Pulse Width, HIGH or LOW
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
TA = +25°C CL = 50 pF
TA = -40°C to +85°C CL = 50 pF Units
(V) (Note 15) 5.0 5.0 5.0
Guaranteed Minimum 3 .0 1 .5 4 .0 3.0 1.5 4.0 ns ns ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF Conditions VCC = 5.0V VCC = 5.0V
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