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Details, datasheet, quote on part number:74ACTQ16374SSCX
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Datasheet text preview:
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
June 1991 Revised November 1999
74ACTQ16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The ACTQ16245 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Buffered Positive edge-triggered clock s Separate control logic for each byte s 16-bit version of the ACTQ374 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number 74ACTQ16374SSC 74ACTQ16374MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram Logic Symbol
Pin Descriptions
Pin Description Names O En CP n I0I15 O0O15 Output Enable Input (Active LOW) Clock Pulse Input Inputs Outputs
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010935
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74ACTQ16374
Functional Description
The ACTQ16374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Truth Tables
Inputs CP 1 Outputs I0I7 H L X X O0O7 H L (Previous) Z Outputs I8I15 H L X X O8O15 H L (Previous) Z
L X
OE1 L L L H Inputs
CP 2
L X
OE2 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X= Immaterial Z = HIGH Impedance = LOW-to-HIGH Transition
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
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74ACTQ16374
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Storage Temperature ± 50 mA -65°C to +150°C -20 mA +20 mA -0.5V to VCC + 0.5V ±50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter V CC (V) 4.5 5.5 4 .5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4 .5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level 5.5 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5 .0 5.0 5.0 0 .5 -0.5 0.8 -1.0 0.6 8.0 0.001 0.001 TA = +25°C Typ 1 .5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ± 0.5 ± 0.1 TA = -40°C to +85°C Guaranteed Limits 2 .0 2.0 0.8 0.8 4.4 5.4 3 .76 4 .76 0 .1 0.1 0 .44 0 .44 ± 5.0 ± 1.0 1.5 80.0 75 - 75 µA µA mA µA mA mA V V V V V V V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) VOH - 1.0 VOH - 1.8 1.7 1.2 2.0 0.8 Figure 1, Figure 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7)
VOH + 1.0 VOH + 1.5
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n - 1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (VILD).
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74ACTQ16374
AC Electrical Characteristics
VCC Symbol fMAX tPLH tP H L tPZH tPZL tP H Z tPLZ
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = +25°C CL = 50 pF Min 71 3.1 3.0 2.5 3.0 2.1 2.0 5.3 5 .1 4.7 5 .4 5.1 4 .8 7.9 7.3 7.4 8.0 7.9 7.4 Typ Max
TA = -40°C to +85°C CL = 50 pF Min 67 3.1 3 .0 2.5 2 .0 2.1 2 .0 8.4 7.8 7.9 8.5 8.2 7.9 Max MHz ns ns ns Units
Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time Output Disable Time
(V) (Note 8) 5.0 5.0 5.0 5.0
AC Operating Requirements
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Input to Clock Hold Time, HIGH or LOW Input to Clock CP Pulse Width, HIGH or LOW
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.
TA = +25°C CL = 50 pF Typ 0 .7 0 .8 1 .5 3.0 1.0 5.0
TA = -40°C to +85°C CL = 50 pF Guaranteed Limits 3 .0 1 .0 5 .0 ns ns ns Units
(V) (Note 9) 5.0 5.0 5.0
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74ACTQ16374
Extended AC Electrical Characteristics
TA = -40°C to +85°C CL = 50 pF Symbol Parameter 16 Outputs Switching (Note 10) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 12) tOSLH (Note 12) tOST (Note 12) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Pin to Pin Skew LH/HL Data to Output Output Disable Time Propagation Delay Data to Output Output Enable Time 4.7 4.6 3.5 3.8 3.4 3.1 Typ M ax 13.3 11.4 10.4 10.9 8.5 8 .1 1.3 2.1 4.0 Min 6.6 6 .4 (Note 13) (Note 14) TA = -40°C to +85°C CL = 250 pF (Note 11) Max 16.3 15.5 ns ns ns ns ns ns Units
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 14: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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