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Part: 74ACTQ16543
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: 16-Bit Registered Transceiver With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74ACTQ16543 datasheet File size : 232 kB
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74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs
December 1991 Revised December 1998
74ACTQ16543 16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceivers containing two sets of D-type registers for temporary storage of data flowing in either direction. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ACTQ16543 utilizes Fairchild Quiet SeriesTM technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control and undershoot corrector for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Separate controls for data flow in each direction s Back-to-back registers for storage Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ543 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number 74ACTQ16543SSC 74ACTQ16543MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEABn OEBAn CEAB n CEBA n LEABn LEBAn A0A15 B0B15 Descriptions A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs
FACTTM, Quiet SeriesTM, FACT Quiet SeriesTM and GTOTM are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010967.prf
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74ACTQ16543
Connection Diagram
Pin Assignment for SSOP and TSSOP
Functional Description
The ACTQ16543 contains sixteen non-inverting transceivers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The following description applies to each byte. For data flow from A to B, for example, the A-to-B Enable (CEABn) input must be LOW in order to enter data from A0A15 or take data from B0B15, as indicated in the Data I/O Control Table. With CEABn LOW, a LOW signal on the A-to-B Latch Enable (LEABn) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEABn signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEABn and OEABn both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA n, LEBAn and OEBAn inputs.
Data I/O Control Table
Inputs CEABn H X L X L LEABn X H L X X OEABn X X X H L Latch Status (Byte n) Latched Latched Transparent -- -- Output Buffers (Byte n) High Z -- -- High Z Driving
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
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74ACTQ16543
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ACTQ16543
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Storage Temperature ±50 mA -65°C to +150°C -20 mA +20 mA -0.5V to VCC + 0.5V ±50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage V CC (V) 4.5 5 .5 4.5 5 .5 4.5 5 .5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5 .5 4.5 5.5 IOZT IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum I/O Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package.
TA = +25°C Typ 1 .5 1.5 1 .5 1.5 4.49 5.49 2.0 2 .0 0 .8 0 .8 4 .4 5.4 3 .86 4 .86 0.001 0.001 0 .1 0 .1 0 .36 0 .36 ± 0.5 ± 0.1 0.6 8 .0
TA = -40°C to+85°C Guaranteed Limits 2 .0 2.0 0 .8 0.8 4.4 5 .4
Units V V V
Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 µA VIN = VILor VIH
3 .76 4 .76 0 .1 0.1
V V
IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 µA VIN = VILor VIH
0 .44 0 .44 ± 5.0 ± 1.0 1 .5 80.0 75 - 75
V µA µA mA µA mA mA V V V V V V
IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7)
5 .5 5.5 5 .5 5.5 5 .5 5.0 5.0 5 .0 5 .0 5.0 5.0 0 .5 -0.5 VOH + 1.0 VOH - 1.0 1.7 1.2
0.8 - 0 .8 VOH + 1.5 VOH - 1.8 2.0 0.8
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74ACTQ16543
DC Electrical Characteristics
(Continued)
Note 5: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n - 1) inputs switching 0V to 3V Input under test switching 3V to threshold (VILD).
AC Electrical Characteristics
VCC Symbol Parameter (V) (Note 8) tPLH tP H L tPLH tP H L tPZH tPZL Propagation Delay Transparent Mode An to Bnor Bn to An Propagation Delay LEBAn, LEABn to An, Bn Output Enable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn tP H Z tPLZ Output Disable Time OEBAn or OEABn to An or Bn CEBAn or CEABn to An or Bn
Note 8: Voltage Range 5.0 is 5.0V ±0.5V.
TA = +25°C CL = 50 pF Min 3.8 3.5 4.7 Typ 5.9 5.5 6.9 6 .3 6 .3 7 .3 Max 8 .3 7 .9 9 .8 9 .0 9.2 10.3
TA = -40°C to +85°C CL = 50 pF M in 3.0 2.6 3.4 3.1 3.0 3.6 Max 9 .0 8 .5 10.8 9 .8 9.9 10.3 ns ns ns Units
5.0
5.0
3.9 4.2
5.0
4.9
2.8 5.0 2.6
5 .2 5 .0
8.0 7 .6
2.1 2.0
8.3 8 .1 ns
AC Operating Requirements
V CC Symbol Parameter (V) (Note 9) tS tH tW Setup Time, HIGH or LOW An or Bn to LEBAn or LEABn Hold Time, HIGH or LOW An or Bn to LEBAn or LEABn Latch Enable, B to A Pulse Width, LOW
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
TA = +25°C CL = 50 pF Typ 3.0
TA = -40°C to +85°C CL = 50 pF Guaranteed Minimum 3 .0 ns Units
5 .0
5 .0
1.5
1 .5
ns
5 .0
4.0
4 .0
ns
5
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