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Part: 74ALVCH162374T
Category:
Description: 74ALVCH162374 - Low Voltage 16-Bit D-type Flip-flop With Bushold And 26 Ohm Series Resistors in Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74ALVCH162374T datasheet File size : 67 kB
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Datasheet text preview:
74ALVCH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
September 2001 Revised February 2002
74ALVCH162374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26 Series Resistors in Outputs
General Description
The ALVCH162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The ALVCH162374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH162374 is also designed with 26 series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. The 74ALVCH162374 is designed for low voltage (1.65V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74ALVCH162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold data inputs eliminates the need for external pull-up/pull-down resistors s 26 series resistors in outputs s tPD (CLK to O n) 4.6 ns max for 3.0V to 3.6V VCC 5.4 ns max for 2.3V to 2.7V VCC 9.6 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V
Ordering Code:
Order Number 74ALVCH162374T Package Number MTD48 Package Descriptions 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn CP n I0I15 O0O15 Description Output Enable Input (Active LOW) Clock Pulse Input Bushold Inputs Outputs
© 2002 Fairchild Semiconductor Corporation
DS500628
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74ALVCH162374
Connection Diagram
Truth Tables
Inputs CP 1 Outputs I0I7 H L X X O0O7 H L O0 Z Outputs I8I15 H L X X O8O15 H L O0 Z OE1 L L L H Inputs CP 2
L X
L X
OE2 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, control inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP
Functional Description
The 74ALVCH162374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVCH162374
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA ±50 mA ±100 mA -65°C to +150°C
Recommended Operating Conditions (Note 3)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 3: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40°C to +85°C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 µA IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 µA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II II(HOLD) Input Leakage Current Bushold Input Minimum Drive Hold Current 0 VI 3.6V VIN = 0.58V VIN = 1.07V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 0 < VO 3.6V IOZ ICC ICC 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3.0 2.7 3 3.6 1.65 1.65 2.3 2.3 3.0 3.0 3.6 3.6 3.6 3 - 3.6 25 - 25 45 - 45 75 - 75 ±500 ±10 40 750 µA µA µA µA VCC - 0.2 1.2 1.9 1.7 2 .4 2 2 0.2 0.45 0 .4 0.55 0 .5 5 0 .6 0 .8 ±5.0 µA V V Min 0.65 x VCC 1 .7 2 .0 0.35 x VCC 0 .7 0 .8 V V M ax Units
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74ALVCH162374
AC Electrical Characteristics
TA = -40°C to +85°C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V ± 0.3V Min fCLOCK tW tS tH fMAX tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Clock Frequency Pulse Width Setup Time Hold Time Maximum Clock Frequency Propagation Delay Output Enable Time Output Disable Time 3 .3 1.9 0.5 150 1 .0 1.0 1.2 4.6 5.2 4.5 Max 150 3.3 2.2 0 .5 150 5 .4 6.4 5 VCC = 2.7V Min Max 150 3 .3 2.1 0.6 150 1.0 1.0 1.0 5 .4 6.5 5.6 CL = 30 pF VCC = 2.5V ± 0.2V Min Max 150 4.0 2.5 1 .0 100 1.5 1.5 1.5 9 .6 9.8 7.9 VCC = 1.8V ± 0.15V Min Max 100 MHz ns ns ns MHz ns ns ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Control Data Conditions VI = 0V or VCC VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 0 pF Outputs Disabled f = 10 MHz, CL = 0 pF TA = +25°C VCC 3.3 3.3 3.3 3.3 2.5 3.3 2.5 Typical 3 6 7 31 28 11 10 pF pF pF Units
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74ALVCH162374
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50) Symbol Vmi Vmo VX VY VL VCC 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V ± 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and tREC Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
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