|
|
Part: 74F374SCX
Category:
Description: Octal D-type Flip-flop With 3-STATE Outputs
Company: Fairchild Semiconductor
Datasheet: Download 74F374SCX datasheet File size : 222 kB
Request For quote: Find where to buy 74F374SCX
Datasheet text preview:
74F374 Octal D-Type Flip-Flop with 3-STATE Outputs
May 1988 Revised September 2000
74F374 Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops.
Features
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number 74F374SC 74F374SJ 74F374MSA 74F374PC Package Number M20B M20D MSA20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009524
www.fairchildsemi.com
74F374
Unit Loading/Fan Out
U.L. Pin Names D0D7 CP OE O0O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/-0.6 mA 20 µA/-0.6 mA 20 µA/-0.6 mA
150/40 (33.3) -3 mA/24 mA (20 mA)
Functional Description
The 74F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affected the state of the flipflops.
Truth Table
Inputs Dn H L X CP Internal OE L L H Register H L X Output On H L Z
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74F374
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65°C to +150°C -55°C to +125°C -55°C to +150°C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0°C to +70°C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current 55 -60 4.75 3.75 -0.6 50 -50 -150 500 86 10% VCC 2.5 2.4 2.7 2.7 0.5 5.0 7.0 50 V µA µA µA V µA mA µA µA mA µA mA Min Max Max Max 0 .0 0 .0 Max Max Max Max 0.0V Max V Min M in 2.0 0.8 -1.2 Typ Max Units V V V Min V CC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH Z
3
www.fairchildsemi.com
74F374
AC Electrical Characteristics
TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 100 4.0 4.0 2.0 2.0 2.0 1 .5 VCC = +5.0V CL = 50 pF Typ 140 6.5 6 .5 9.0 5 .8 5 .3 4 .3 8.5 8.5 11.5 7.5 7.0 5.5 Max TA = -55°C to +125°C VCC = +5.0V CL = 50 pF M in 60 4.0 4 .0 2.0 2 .0 2 .0 1 .5 10.5 11.0 14.0 10.0 8.0 7 .5 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF M in 70 4.0 4.0 2.0 2.0 2.0 1.5 10.0 10.0 12.5 8.5 8.0 6 .5 ns Max MHz ns Units
AC Operating Requirements
TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH( L ) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW 2.0 2.0 2 .0 2.0 7 .0 6 .0 Max TA = -55°C to +125°C VCC = +5.0V M in 2.5 2 .0 2.0 2 .5 7 .0 6.0 M ax TA = 0°C to +70°C VCC = +5.0V Min 2.0 2.0 2.0 2.0 7.0 6.0 ns ns Max Units
www.fairchildsemi.com
4
74F374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
5
www.fairchildsemi.com
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
