|74F377 Octal D-Type Flip-Flop with Clock Enable
The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See 74F273 for master reset version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version
Order Number 74F377SJ 74F377PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code.
U.L. Pin Names CP Q0Q7 Description HIGH/LOW Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs Input IIH/IIL Output IOH/IOL µA/-0.6 mA
Inputs Operating Mode CP Load "1" Load "0" Hold (Do Nothing) Output L No Change No Change CE
H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial = LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL IOS ICEX VID IOD ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Output Short-Circuit Current Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Power Supply Current VCC 5% VCC 10% VCC Min 0.8 -1.2 Typ Max Units µA mA Min Max 0.0 Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -1 mA IOL 20 mA VIN = 2.7V VIN = 7.0V VIN = 0.5V VOUT = 0V VOUT = VCC IID 1.9 µA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded MR = HIGH