|Category||Logic => Flip-Flops => Bipolar->F Family|
|Description||Parallel D-type Register With Enable|
|Datasheet||Download 74F378 datasheet
The a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset.Features
s 6-bit high-speed parallel register s Positive edge-triggered D-type inputs s Fully buffered common clock and enable inputs s Input clamp diodes limit high-speed termination effects s Full TTL and CMOS compatible
Order Number 74F378SJ 74F378PC Package Number M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
U.L. Pin Names CP Q0Q5 Description HIGH/LOW Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Outputs Input IIH/IIL Output IOH/IOL ľA/-0.6 mA
The 74F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When the E input is LOW, new data is entered into the register on the LOW-to-HIGH transition of the CP input. When the E input is HIGH the register will retain the present data independent of the CP input.H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current VCC 5% VCC 10% VCC Min 0.8 -1.2 Typ Max Units ľA mA Min Max 0.0 Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -1 mA IOL 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID 1.9 ľA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V VOUT VO = LOW
|Related products with the same datasheet|
|Some Part number from the same manufacture Fairchild Semiconductor|
|74F378PC Parallel D-type Register With Enable|
|74F379 Quad Parallel Register With Enable|
|74F37PC Quad 2-Input NAND Buffer|
|74F38 Quad 2-Input NAND Buffer (Open Collector)|
|74F381 4-Bit Arithmetic Logic Unit|
|74F38PC Quad 2-Input NAND Buffer (Open Collector)|
|74F398 Quad 2-Port Register|
|74F401 CRC Generator/checker|
|74F402 Serial Data Polynomial Generator/checker|
|74F403A First-in First-out (FIFO) Buffer Memory|
|74F413 64 X 4 First-in First-out Buffer Memory With Parallel I/o|
|74F433 First-in First-out (FIFO) Buffer Memory|
|74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input And-or-invert Gate|
|74F521 8-Bit Identity Comparator|
|74F524 8-Bit Registered Comparator|
|74F533 Octal Transparent Latch With 3-STATE Outputs|
|74F534 Octal D-type Flip-flop With 3-STATE Outputs|
|74F537 1-of-10 Decoder With 3-STATE Outputs|
|74F538 1-of-8 Decoder With 3-STATE Outputs|
54F04FM : Hex Inverter. This device contains six independent gates, each of which performs the logic INVERT function. See Section 0 Military Package Number N14A 54F04DM (Note M14D 54F04FM (Note 2) 54F04LM (Note 14-Lead (0.300" Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0.150" Wide) Molded Small Outline, JEDEC 14-Lead (0.300" Wide) Molded Small Outline,.
74F521 : Bipolar->F Family. 8-Bit Identity Comparator. The is an expandable 8-bit comparator. It compares two words up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion input IA=B also serves as an active LOW enable input. s Compares two 8-bit words 6.5 ns typ s Expandable to any word length s 20-pin package Order Number 74F521MSA 74F521PC Package Number MSA20.
CD74ACT240E : Inverting Buffers and Drivers. ti CD74ACT240, Octal Inverting Buffers/line Drivers With 3-State Outputs.
DM74LS573 : Bipolar->LS Family. Octal D-type Latch With 3-STATE Outputs. The is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the DM74LS373, but has different pinouts. s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally.
HD74LVC540A : CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage. Octal Buffers/line Drivers With 3-state Outputs.
IDT74ALVC16245 : Bus Oriented Circuits. 3.3v CMOS 16-bit Bus Transceiver With 3-state Outputs.
MC100H607FNR2 : BBG Ecl Trnslatr Hex, Package: Plcc, Pins=28. The a 6bit, registered PECL to TTL translator. The device differential PECL inputs for both data and clock. The TTL outputs feature 48mA sink, 24mA source drive capability for driving high fanout loads or transmission lines. The asynchronous master reset control is an ECL level input. With its differential PECL inputs and TTL outputs the H607 device.
MC14024B : CMOS/BiCMOS->4000 Family. 7-stage Ripple Counter. The a 7stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered. Diode Protection on All Inputs Output Transitions Occur on the Falling Edge of the Clock Pulse Supply.
MC74F657ADW/BDW : Octal Bidirectional Transceiver With 8-bit Parity Generator Checker ( 3-state Outputs ).
MM74C86 : CMOS/BiCMOS->4000 Family. Quad 2-Input Exclusive-OR GATE. The MM74C86 employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially.
SK100EL52W : Differential Data And Clock D Flip-flop. The is a differential data, differential clock D flip-flop. This device is fully compatible with MC10/100EL52 and functionally equivalent to the E452 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E452, the EL52W is ideally suited for those applications which require the ultimate.
SN54ACT374 : CMOS/BiCMOS->AC/ACT Family. Octal D-type Edge-triggered Flip-flops With 3-state Outputs.
SN54ALS653FK : Octal Bus Transceivers And Registers With 3-state Outputs. Bus Transceivers/Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Choice of True or Inverting Data Paths Choice 3-State or Open-Collector Outputs to A Bus Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs.
SN74ABT18646PM : ti SN74ABT18646, Scan Test Devices With 18-Bit Bus Transceivers And Registers.
SN74LVTH16244B : 3.3-v Abt 16-bit Buffers/drivers With 3-state Outputs. Members of the Texas Instruments Widebus TM Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down 2.7 V Typical VOLP (Output Ground Bounce) V at VCC = 25°C Ioff.
SN74SSTVF16859GR : Memory Drivers and Transceivers (HSTL, SSTL, SSTV). ti SN74SSTVF16859, 13-Bit to 26-Bit Registered Buffer With SSTL_2 Inputs And Outputs.
A1240A-1PG132E : FPGA, 684 CLBS, 4000 GATES, 63 MHz, CPGA132. s: System Gates: 4000 ; Logic Cells / Logic Blocks: 684 ; Package Type: Other, CERAMIC, PGA-132 ; Logic Family: CMOS ; Pins: 132 ; Internal Frequency: 63 MHz ; Propagation Delay: 5.2 ns ; Supply Voltage: 5V.
SN74S161N : S SERIES, SYN 4-BIT UP BINARY COUNTER, PDIP16. s: Counter Type: BINARY COUNTER ; Counter Category: Synchronous ; Counter Direction: UP ; Supply Voltage: 5V ; Package Type: DIP, DIP-16 ; Logic Family: TTL, S ; Number of Pins: 16 ; Number of Stages (Bits): 4 bits.
933714400652 : HC/UH SERIES, HEX 1-INPUT INVERT GATE, PDSO14. s: Gate Type: NOT ; Supply Voltage: 4.5 ; Logic Family: CMOS ; Inputs: 1 ; Propagation Delay: 190 ns ; Operating Temperature: -40 to 125 C (-40 to 257 F) ; Pin Count: 14 ; IC Package Type: Other, SOT-108-1, SO-14.