The a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset.
s Edge triggered D-type inputs s Buffered positive edge-triggered clock s Buffered common enable input s True and complement outputs
Order Number 74F379SJ 74F379PC Package Number M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
U.L. Pin Names CP Q0Q3 Description HIGH/LOW Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Flip-Flop Outputs Complement Outputs Input IIH/IIL Output IOH/IOL µA/-0.6 mA
The 74F379 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flipflops. When the E is input HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed.
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current VCC 5% VCC 10% VCC Min 0.8 -1.2 Typ Max Units µA mA Min Max 0.0 Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -1 mA IOL 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID 1.9 µA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V VOUT VO = LOW