Part  74F382PC 
Category  
Title  Bipolar>F Family 
Description  4Bit Arithmetic Logic Unit 
Company  Fairchild Semiconductor 
Datasheet  Download 74F382PC datasheet

Cross ref.  Similar parts: SN54F521, SN74F521 
Quote 
Features, Applications 
The 74F382 performs three arithmetic and three logic operations on two 4bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For highspeed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet. Featuress Performs six arithmetic and logic functions s Selectable LOW (clear) and HIGH (preset) functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic Order Number 74F382SJ 74F382PC Package Number M20D N20A Package Description 20Lead Small Outline Integrated Circuit (SOIC), JEDEC MS013, 0.300 Wide 20Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20Lead Plastic DualInLine Package (PDIP), JEDEC MS001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pin Names + 4 OVR F0F3 Description A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL µA/3.0 mA Signals applied to the Select inputs S0S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the ExclusiveOR + 3 and 4; a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure 1. Operation Clear B Minus A Minus B A Plus B AB A+B AB PresetInputs Function CLEAR B MINUS L Cn MINUS PLUS AB A+B AB PRESET 
Related products with the same datasheet 
74F382SC 
74F382SCX 
74F382SJ 
Some Part number from the same manufacture Fairchild Semiconductor 
74F382SC 4Bit Arithmetic Logic Unit 
74F38PC Quad 2Input NAND Buffer (Open Collector) 
74F398 Quad 2Port Register 
74F399 
74F401 CRC Generator/checker 
74F402 Serial Data Polynomial Generator/checker 
74F403A Firstin Firstout (FIFO) Buffer Memory 
74F413 64 X 4 Firstin Firstout Buffer Memory With Parallel I/o 
74F433 Firstin Firstout (FIFO) Buffer Memory 
74F51 Dual 2Wide 2Input; 2Wide 3Input Andorinvert Gate 
74F521 8Bit Identity Comparator 
74F524 8Bit Registered Comparator 
74F533 Octal Transparent Latch With 3STATE Outputs 
74F534 Octal Dtype Flipflop With 3STATE Outputs 
74F537 1of10 Decoder With 3STATE Outputs 
74F538 1of8 Decoder With 3STATE Outputs 
74F539 Dual 1of4 Decoder With 3STATE Outputs 
74F540 Octal Buffer/line Driver With 3STATE Outputs (Inverting) 
74F541 Octal Buffer/line Driver With 3STATE Outputs 
74F543 Octal Registered Transceiver 
74F544 