|Category||Interface and Interconnect|
|Datasheet||Download 74F401 datasheet
The 74F401 Cycle Redundancy Check (CRC) Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals (reverse polynomials). Automatic right justification is incorporated for polynomials of degree less than 16. Separate clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. Another control input inhibits feedback during check word transmission. The 74F401 is fully compatible with all TTL families.Features
s Eight selectable polynomials s Error indicator s Separate preset and clear controls s Automatic right justification s Fully compatible with all TTL logic families s 14-pin package s 9401 equivalent s Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Order Number 74F401SC 74F401PC Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Names D CP CWE Q ER Description Polynomial Select Inputs Data Input Clock Input (Operates on HIGH-to-LOW Transition) Check Word Enable Input Preset (Active LOW) Input Master Reset (Active HIGH) Input Data Output Error Output U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL mA/20 mA
The a 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1 and S2. The 74F401 consists a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code presented at inputs S0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data inputs (D), using the HIGH-to-LOW transition of the Clock input (CP). This data is gated with the most significant output (Q) of the register, and controls the Exclusive OR gates Figure 1. The Check Word Enable (CWE) must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure 2. To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the by a HIGH-to-LOW transition of CP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH. A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P) asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case or 8-bit check polynomials only the most significant or 8 register bits are set and the remaining bits are cleared.TABLE 1. Select Code S1 S0 Polynomial 1 LRC-8 CRC-CCITT REVERSE CRC-12 Remarks CRC-16 REVERSE
Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2: 74F401 must be reset or preset before each computation. Note 3: CRC check bits are generated and appended to data bits.
|Related products with the same datasheet|
|Some Part number from the same manufacture Fairchild Semiconductor|
|74F401CW CRC Generator/checker|
|74F402 Serial Data Polynomial Generator/checker|
|74F403A First-in First-out (FIFO) Buffer Memory|
|74F413 64 X 4 First-in First-out Buffer Memory With Parallel I/o|
|74F433 First-in First-out (FIFO) Buffer Memory|
|74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input And-or-invert Gate|
|74F521 8-Bit Identity Comparator|
|74F524 8-Bit Registered Comparator|
|74F533 Octal Transparent Latch With 3-STATE Outputs|
|74F534 Octal D-type Flip-flop With 3-STATE Outputs|
|74F537 1-of-10 Decoder With 3-STATE Outputs|
|74F538 1-of-8 Decoder With 3-STATE Outputs|
|74F539 Dual 1-of-4 Decoder With 3-STATE Outputs|
|74F540 Octal Buffer/line Driver With 3-STATE Outputs (Inverting)|
|74F541 Octal Buffer/line Driver With 3-STATE Outputs|
|74F543 Octal Registered Transceiver|
|74F545 Octal Bidirectional Transceiver With 3-STATE Inputs/outputs|
|74F552 Octal Registered Transceiver With Parity And Flags|
|74F563 Octal D-type Latch With 3-STATE Outputs|
|74F564 Octal D-type Flip-flop With 3-STATE Outputs|
DM74AS640 : Bus Oriented Circuits Octal 3-STATE Octal Bus Transceiver
NDS0610 : Enhancement P-Channel P-channel Enhancement Mode Field Effect Transistor
SA60CA : 500 Watt Transient Voltage Suppressors
CNY17F1TVM : Phototransistor Optocouplers
NM24C02FLZVMT8 : 2k-bit Standard 2-wire Bus
HLMP6600AZR : LEDs -; LED RED DIFF SQ 5V RES 1.9MM ZB Specifications: Color: Red ; Lens Style/Size: Round, 1.8mm ; Millicandela Rating: 5mcd ; Voltage - Forward (Vf) Typ: 5V ; Wavelength - Dominant: 626nm ; Wavelength - Peak: 635nm ; Current - Test: 9.6mA ; Viewing Angle: 90° ; Lens Type: Diffused, Tinted ; Luminous Flux @ Current - Test: 9 mlm ; Packa
FQB34P10TM_F085 : Fet - Single Discrete Semiconductor Product 33.5A 100V 3.75W Surface Mount; MOSFET P-CH 100V 33.5A D2PAK Specifications: Mounting Type: Surface Mount ; FET Type: MOSFET P-Channel, Metal Oxide ; Drain to Source Voltage (Vdss): 100V ; Current - Continuous Drain (Id) @ 25° C: 33.5A ; Rds On (Max) @ Id, Vgs: 60 mOhm @ 16.75A, 10V ; Input Capacitance (Ciss) @ Vds: 2910pF @ 25V ; Power - Max: 3.75W ; Packagi
FGPF50N33BTTU : IGBT, TO-220AB Specifications: Transistor Type / Technology: IGBT ; Package Type: TO-220, ROHS COMPLIANT, TO-220F, 3 PIN
FDMS86300DC : MOSFET N CH 80V 24A 8-PQFN Fairchild Semiconductor PowerTrench® MOSFET technology enables high power density for high-efficiency solutions providing the lowest RDS(ON) available, improved FOM and lower power dissipation. Features Superior switching performance and low switching noise Lower switch node
70V7288 : Multi-Ports. 64K X 16 Asynchronous Bank-switchable Dual-port SRAM. HIGH-SPEED x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS x 16 Bank-Switchable Dual-Ported SRAM Architecture Four independent x 16 banks 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15ns User-controlled input pins included for bank selects Independent port controls with asynchronous address & data.
74F402 : Serial Data Polynomial Generator/checker. The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC16, CRC-CCITT.
DS92LV1212A : Bus LVDS Serializer / Deserializer Devices. DS92LV1212A - 16 MHZ - 40 MHZ 10-Bit Bus LVDS Random Lock Deserializer With Embedded Clock Recovery, Package: SSOP-EIAJ, Pin Nb=28.
HIP4081 : 80V/2.5A Peak, High Frequency Full Bridge Fet Driver. 80V/2.5A Peak, High Frequency Full Bridge FET Driver The is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081 can switch at frequencies to 1MHz and is well.
LM87 : Serial Interface System Hardware Monitor With Remote Diode Temperature Sensing.
LMS1487 : LMS1487 - 5V Low Power RS-485 / RS-422 Differential Bus Transceiver, Package: Soic Narrow, Pin Nb=8.
MAX9311EVKIT : MAX9311EVKIT Evaluation Kit For The MAX9311/MAX9314. The MAX9311 evaluation kit (EV kit) includes the MAX9311 low-skew, 1-to-10 differential driver designed for clock distribution. The MAX9311 EV kit supports LVECL/LVPECL testing to 3GHz. The kit allows selection of two sources and reproduces the selected signal at 10 identical differential outputs. Inputs can be differential or single ended. Single-ended.
PACS1284-04QR : P/active Ieee 1284 Ecp/epp Termination Network.
SN65LVDS048D : ti SN65LVDS048, LVDS Quad Differential Line Receiver. >400 Mbps (200 MHz) Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ) Propagation Delay Times 2.7 ns (Typ) 3.3 V Power Supply Design High-Impedance LVDS Inputs on Power Down Low-Power Dissipation 3.3 V Static) Accepts Small Swing (350 mV) Differential Signal Levels Supports.
SN75116D : Non-Standard Line Circuits. ti SN75116, Differential Line Transreceiver.
uA9636AC : Dual Line Driver With Adjustable Slew Rate. uA9636AC DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-423-B and -232-E and ITU Recommendations V.10 and V.28 Output Slew Rate Control Output Short-Circuit-Current Limiting Wide Supply Voltage Range 8-Pin Package Designed to Be Interchangeable With National DS9636A The is a dual, single-ended.
AD9396 : Analog/DVI Dual-Display Interface The AD9396 offers designers the flexibility of an analog interface and digital visual interface (DVI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP). The AD9396 is a complete 8-bit, 150 MSPS monolithic analog interface optimized for capturing component.
MAX253 : Transformer Driver For Isolated RS-485 Interface The MAX253 is a monolithic oscillator/power-driver, specifically designed to provide isolated power for an isolated RS-485 or RS-232 data interface. It drives a center-tapped transformer primary from a 5V or 3.3V DC power supply. The secondary can be wound to provide any isolated voltage needed at power.
DS90UB914Q : DS90UB913Q/4Q 10-100MHz 10/12-Bit FPD-Link III SER/DES The DS90UB913Q/DS90UB914Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB913Q/914Q chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional.