The 74F401 Cycle Redundancy Check (CRC) Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals (reverse polynomials). Automatic right justification is incorporated for polynomials of degree less than 16. Separate clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. Another control input inhibits feedback during check word transmission. The 74F401 is fully compatible with all TTL families.
s Eight selectable polynomials s Error indicator s Separate preset and clear controls s Automatic right justification s Fully compatible with all TTL logic families s 14-pin package s 9401 equivalent s Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Order Number 74F401SC 74F401PC Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Names D CP CWE Q ER Description Polynomial Select Inputs Data Input Clock Input (Operates on HIGH-to-LOW Transition) Check Word Enable Input Preset (Active LOW) Input Master Reset (Active HIGH) Input Data Output Error Output U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL mA/20 mA
The a 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1 and S2. The 74F401 consists a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code presented at inputs S0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data inputs (D), using the HIGH-to-LOW transition of the Clock input (CP). This data is gated with the most significant output (Q) of the register, and controls the Exclusive OR gates Figure 1. The Check Word Enable (CWE) must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure 2. To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the by a HIGH-to-LOW transition of CP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH. A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P) asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case or 8-bit check polynomials only the most significant or 8 register bits are set and the remaining bits are cleared.
TABLE 1. Select Code S1 S0 Polynomial 1 LRC-8 CRC-CCITT REVERSE CRC-12 Remarks CRC-16 REVERSE
Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2: 74F401 must be reset or preset before each computation. Note 3: CRC check bits are generated and appended to data bits.