The an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing "register equal to bus", "register greater than bus" and "register less than bus" are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.
s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus comparator with "equal to", "greater than" and "less than" outputs s Cascadable in groups of eight bits s Open-collector expansion comparator outputs for AND-wired
Order Number 74F524SC 74F524PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
U.L. Pin Names , S1 C/SI M I/O0I/O7 Description HIGH/LOW Mode Select Inputs Status Priority or Serial Data Input Clock Pulse Input (Active Rising Edge) Status Enable Input (Active LOW) Compare Mode Select Input Parallel Data Inputs or 3-STATE Parallel Data Outputs C/SO EQ GT
Input IIH/IIL Output IOH/IOL mA (20 mA) mA/20 mA (Note /20 mA (Note /20 mA (Note /20 mA
Status Priority or Serial Data Output Register Less Than Bus Output Register Equal Bus Output Register Greater Than Bus Output
L H Magnitude Compare Twos Complement Compare Operation
L H Operation Hold--Retains Data in Shift Register Read--Read Contents in Register onto Data Bus, Data Remains in Register Unaffected by Clock Shift--Allows Serial Shifting on Next Rising Clock Edge Load--Load Data on Bus into Register
(Hold Mode) Inputs SE C/SI Data Comparison X OAOH > I/O0I/O7 OAOH = I/O0I/O7 OAOH < I/O0I/O7 OAOH > I/O0I/O7 OAOH = I/O0I/O7 OAOH I/O0I/O7 EQ Outputs GT LT C/SO
1 = HIGH if data are equal, otherwise LOW H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0I/O7. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The operation of the shift register is controlled by two signals S0 and S1 according to the Select Truth Table. The 3-STATE parallel output buffers are enabled only in the Read mode. One port an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are "greater than", (GT), "less than" (LT), or "equal to" (EQ) the data on the input bus. A HIGH signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode control input (M) allows selection between a straightforward magnitude compare or a comparison between twos complement numbers. For "greater than" or "less than" detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the "greater than" and "less than" outputs. The C/SO output will be forced HIGH if the "equal to" status condition exists, otherwise C/SO will be held LOW. These facilities enable the to be cascaded for word length greater than eight bits. Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own SE input (see Figure 1). The C/SI input of the most significant device is held HIGH while the SE input of the least significant device is held LOW. The corresponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving "n" cascaded 74F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take + 6(n-2) ns.