|Category||Logic => Latches => Bipolar->F Family|
|Description||Octal Transparent Latch With 3-STATE Outputs|
|Datasheet||Download 74F533 datasheet
|Cross ref.||Similar parts: S54F533F/883B, S54F533F/883C, SN74F533DW3, SN74F533N3|
The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted.Features
s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373
Order Number 74F533SJ 74F533PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
U.L. Pin Names OE O0O7 Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) Complementary 3-STATE Outputs Description HIGH/LOW Input IIH/IIL Output IOH/IOL µA/-0.6 mAH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Output O0 Z The 74F533 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current VCC µA mA Min Max 0.0 Max 0.0V Max V Min 0.8 -1.2 Typ Max Units V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -3 mA IOH -1 mA IOH -3 mA IOL 24 mA VIN = 2.7V VIN = 7.0V VIN = 5.5V VOUT = VCC IID 1.9 µA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT VO = HIGH Z
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