|Category||Logic => Flip-Flops => Bipolar->F Family|
|Description||Octal D-type Flip-flop With 3-STATE Outputs|
|Datasheet||Download 74F534 datasheet
|Cross ref.||Similar parts: 54F534/BRA, 54F534/BRAJC, M38510/34106BRA, S54F534F/883B, S54F534F/883C, SN74F534ADW, SN74F534AN, SN74F534DW3|
The is a high speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops. The 74F534 is the same as the 74F374 except that the outputs are inverted.Features
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications
Order Number 74F534SJ 74F534PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
U.L. Pin Names OE O0O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) Complementary 3-STATE Outputs Description HIGH/LOW Input IIH/IIL Output IOH/IOL µA/-0.6 mA
The 74F534 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Clock Transition O0 = Value stored from previous clock cycle
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current VCC µA mA Min Max 0.0 Max 0.0V Max V Min 0.8 -1.2 Typ Max Units V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -3 mA IOH -1 mA IOH -3 mA IOL 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID 1.9 µA All Other Pins Grounded VIOD 1.50 µA All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT VO = HIGH Z
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