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Details, datasheet, quote on part number: 74F538SJ
TitleBipolar->F Family
Description1-of-8 Decoder With 3-STATE Outputs
CompanyFairchild Semiconductor
DatasheetDownload 74F538SJ datasheet
QuoteFind where to buy 74F538SJ


Features, Applications

The 74F538 decoder/demultiplexer accepts three Address (A0A2) input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion 1-of 32 decoding with four packages, or for data demultiplexing or 1-of-16 destinations.


s Output polarity control s Data demultiplexing capability s Multiple enables for expansion s 3-STATE outputs

Order Number 74F538SJ 74F538PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Pin Names OE2 O0O7 Address Inputs Enable Inputs (Active LOW) Enable Inputs (Active HIGH) Polarity Control Input Output Enable Inputs (Active LOW) 3-STATE Outputs Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL A/-0.6 mA

Inputs Function High Impedance Disable OE1 Active HIGH Output = L) Active LOW Output = H)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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0-C     D-L     M-R     S-Z     0-C     D-L     M-R     S-Z