Details, datasheet, quote on part number: 74F544
Part74F544
CategoryLogic => Bus Interface => Bus Oriented Circuits
TitleBus Oriented Circuits
DescriptionOctal Registered Transceiver
CompanyFairchild Semiconductor
DatasheetDownload 74F544 datasheet
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Features, Applications

The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. The 74F544 inverts data in both directions.

Features

s 8-bit octal transceiver s Back-to-back registers for storage s Separate controls for data flow in each direction s A outputs sink 24 mA, B outputs sink 64 mA

Order Number 74F544MSA 74F544SPC Package Number MSA24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

U.L. Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0­A7 Description HIGH/LOW A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-STATE Outputs B0­B7 B-to-A Data Inputs or A-to-B 3-STATE Outputs Input IIH/IIL Output IOH/IOL µA/-650 µA

The 74F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0­A7 or take data from B0­B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from A is similar, but using the CEBA, LEBA and OEBA inputs.

Inputs CEAB LEAB OEAB Latch Status Latched Transparent Output Buffers High Z High Z Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Min VCC 10% VCC 10% VCC 5% VCC 5% VCC VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IBVIT Input HIGH Current Breakdown (I/O) ICEX VID IOD Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current IIL IIH + IOZH IIL + IOZL IOS Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current -60 -100 IZZ ICCH ICCL ICCZ Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current VCC 10% VCC V µA Min V Min Typ Max Units V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA, (except An, Bn) IOH -1 mA (An) IOH -3 mA (An, Bn) IOH -15 mA (Bn) IOH -1 mA (An) IOH -3 mA (An, Bn) IOL 24 mA (An) IOL 64 mA (Bn) VIN = 2.7V (except An, Bn) VIN = 7.0V (except An, Bn) VIN = 5.5V (An, Bn) VOUT = VCC (An, Bn) IID 1.9 µA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V (OEAB, OEBA) VIN = 0.5V (CEAB, CEBA) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V (An) VOUT = 0V (Bn) VOUT = 5.25V (An, Bn) VO = HIGH VO = LOW VO = HIGH Z


 

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