Details, datasheet, quote on part number: 74F552
Part74F552
CategoryLogic => Bus Interface => Bus Oriented Circuits
TitleBus Oriented Circuits
DescriptionOctal Registered Transceiver With Parity And Flags
CompanyFairchild Semiconductor
DatasheetDownload 74F552 datasheet
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Features, Applications
74F552 Octal Registered Transceiver with Parity and Flags

The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data B0­B7 is checked.

Features

s 8-Bit bidirectional I/O Port with handshake s Register status flag flip-flops s Separate clock enable and output enable s Parity generation and parity check s B-outputs sink s 3-STATE outputs

Order Number 74F552SC 74F552QC Package Number M28B V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Pin Names FR FS PARITY ERROR CER CES CPR CPS OEBR OEAS Description A-to-B Port Data Inputs or B-to-A 3-STATE B-to-A Transceiver Inputs or A-to-B 3-STATE Output B Port Flag Output A Port Flag Output Parity Bit Transceiver Input or Output Parity Check Output (Active LOW) R Registers Clock Enable Input (Active LOW) S Registers Clock Enable Input (Active LOW) R Registers Clock Pulse Input (Active Rising Edge) S Registers Clock Pulse Input (Active Rising Edge) B Port and PARITY Output Enable (Active LOW) and Clear FR Input (Active Rising Edge) A Port Output Enable (Active LOW) and Clear FS Input (Active Rising Edge) µA/-1.2 mA U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL mA (20 mA) µA/-1.2 mA

Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, provided that the Clock Enable (CER) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B Port I/O pins after the Output Enable (OEBR) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW-to-HIGH. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOW-to-HIGH transition at CPS pin enters the B-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A Port I/O pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal.

(Applies or S Register) Inputs CP CE Internal Function H NC Hold Data Load Data Keep Old Data
(Applies or S Flag Flip-Flop) Inputs Flag Function CP OE Output H L Hold Flag Set Flag Clear Flag
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
or B Outputs L H Function Disable Output Enable Output Enable Output OEBR H L

 

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74F552QC
74F552SC
74F552SCX
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