Details, datasheet, quote on part number: 74F563SC
TitleBipolar->F Family
DescriptionOctal D-type Latch With 3-STATE Outputs
CompanyFairchild Semiconductor
DatasheetDownload 74F563SC datasheet
Cross ref.Similar parts: CD74ACT373, CD74ACT573, CD74HCT373, CD74HCT563, CD74HCT573, CY74FCT2373T, CY74FCT2573T, CY74FCT373T, CY74FCT573T, SN74ABT373
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Features, Applications

The is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device is functionally identical to the 74F573, but has inverted outputs.


s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F573

Order Number 74F563SJ 74F563PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Pin Names OE O0­O7 Data Inputs Latch Enable Input (Active HIGH) 3-STATE Output Enable Input (Active LOW) 3-STATE Latch Outputs Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL ľA/-0.6 mA

The 74F563 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Inputs OE LE Internal L NC Output Function NC High Z High Z High Z Latched Transparent Latched
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)

Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.

Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IOZH IOZL IOS IZZ ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current VCC ľA mA Min Max 0.0 Max 0.0V Max V Min 0.8 -1.2 Typ Max Units V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA IOH -1 mA IOH -3 mA IOH -1 mA IOH -3 mA IOL 24 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID 1.9 ľA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0V VOUT VO = LOW VO = HIGH Z


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