|Category||Logic => Counters => Bipolar->F Family|
|Description||8-Bit Bidirectional Binary Counter With 3-STATE Outputs|
|Datasheet||Download 74F579 datasheet
The is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.Features
s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typical s Supply current 75 mA typical s Guaranteed 4000V minimum ESD protection
Order Number 74F579SJ 74F579PC Package Number M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code.
Pin Names I/O0I/O7 PE U/D MR SR CEP CET CP TC Data Inputs or 3-STATE Outputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Chip Select Input Active (Active LOW) Output Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Terminal Count Output (Active LOW) Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL ľA/-0.2 mA
CS PE CEP CET U/D CP X Function I/Oa to I/Oh in High Z (PE Disabled) I/Oa to I/Oh in High Z Flip-Flop Outputs Appear on I/O Lines Asynchronous Reset for all Flip-Flops Synchronous Reset for all Flip-Flops Parallel Load all Flip-Flops Hold (TC Held HIGH) Count Up Count Down
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition Not = CS and PE should never both be LOW voltage level at the same time.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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