|Category||Logic => Bus Interface => Bus Oriented Circuits|
|Title||Bus Oriented Circuits|
|Description||Inverting Octal Bus Transceiver With 3-STATE Outputs|
|Datasheet||Download 74F623 datasheet
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The is an inverting option of the 74F623.Features
s Designed for asynchronous two-way data flow between busses s Outputs sink mA s Dual enable inputs control direction of data flow s Guaranteed 4000V minimum ESD protection is an inverting option of the 74F623
Order Number 74F623SC 74F623PC Package Number M20B N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.FAST® is a registered trademark of Fairchild Semiconductor Corporation
Pin Names GBA, GAB A0A7 B0B7 Description Enable Inputs A Inputs or 3-STATE Outputs B Inputs or 3-STATE Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL mA/64 mA
The enable inputs GAB and GBA control whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. If both GBA and GAB are disabled (GBA HIGH and GAB LOW), the outputs are in the high impedance state and data is stored at the A and B busses. When GBA is active LOW, B data is sent to the A bus. When GAB is active HIGH, data from the A bus is sent to the B bus. If both enable inputs are active (GBA LOW and GAB HIGH) B data is sent to the A bus while A data is sent to the B bus.Enable Inputs GBA GAB 74F620 B Data to A Bus A Data to B Bus Z B Data to A Bus, A Data to B Bus
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance
Operation 74F623 B Data to A Bus A Data to B Bus Z B Data to A Bus, A Data to B Bus
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) -0.5V to VCC +5.0 mA
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IZZ ICCH ICCL ICCZ ICCH ICCL ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current (74F620) Power Supply Current (74F620) Power Supply Current (74F620) Power Supply Current (74F623) Power Supply Current (74F623) Power Supply Current (74F623) VCC 10% VCC Min 0.8 -1.2 Typ Max Units µA mA Min Max 0.0 Max 0.0V Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN -18 mA (Non I/O Pins) IOH -15 mA (An, Bn) IOL (A n, Bn) VIN = 2.7V VIN = 7.0V (GBA, GAB) VIN = 5.5V (An, Bn) VOUT = VCC IID 1.9 µA All Other Pins Grounded VIOD 150 mV All Other Pins Grounded VIN = 0.5V (Non I/O Pins) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V VOUT VO = HIGH, VIN VO = LOW VO = HIGH VO = HIGH VO = LOW, VIN VO = HIGH Z
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