|Category||Logic => Bus Interface => Bus Oriented Circuits|
|Title||Bus Oriented Circuits|
|Description||Octal Bus Transceiver And Register With 3-STATE Outputs|
|Datasheet||Download 74F646 datasheet
These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register.Features
s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F648 has inverting data paths s 74F646/74F646B have non-inverting data paths is a faster version of the s 3-STATE outputs s 300 mil slim DIP
Order Number 74F648SC 74F648SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Names A0A7 B0B7 CPAB, CPBA SAB, SBA G DIR Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL µA/-650 µA
Inputs DIR CPAB CPBA SAB L X SBA Output Input Data I/O (Note A0A7 B0B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output Bn to An--Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An FunctionH = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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