The is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed memory chip select address decoding. The multiple input enables allow parallel expansion a 1-of-24 decoder using just three LCX138 devices a 1-of-32 decoder using four LCX138 devices and one inverter. The 74LCX138 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
s 5V tolerant inputs to 3.6V VCC specifications provided 6.0 ns tPD max (VCC 10 µA ICC max s Power down high impedance inputs and outputs ±24 mA output drive (VCC 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds mA s ESD performance: Human body model > 2000V Machine model 200V s Leadless DQFN package
Order Number 74LCX138SJ 74LCX138BQ (Preliminary) 74LCX138MTC Package Number M16D MLP016E (Preliminary) MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC 3.5mm 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Pin Names E3 O0O7 Description Address Inputs Enable Inputs Enable Input Outputs
The LCX138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs A1, A2) and, when enabled, provides eight mutually exclusive activeLOW outputs (O0O7). The LCX138 features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. The LCX138 can be used an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active-HIGH or active-LOW state.
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.