Details, datasheet, quote on part number: 74LCX16244
Part74LCX16244
CategoryLogic => Line Driver/Receivers => CMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage
TitleCMOS/BiCMOS->LVT/ALVT/LCX/LPT Family->Low Voltage
DescriptionLow Voltage 16-Bit Buffer/line Driver With 5V Tolerant Inputs And Outputs
CompanyFairchild Semiconductor
DatasheetDownload 74LCX16244 datasheet
Cross ref.Similar parts: 74LCX16244AT, 74LCX16244T, PI74LCX16244A, PI74LCX16244V
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Features, Applications
74LCX16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs

The LCX16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The LCX16244 is designed for low voltage or 3.3V) VCC applications with capability of interfacing a 5V signal environment. The LCX16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.

Features

s 5V tolerant inputs and outputs to 3.6V VCC specifications provided 4.5 ns tPD max, 10 µA ICCQ max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note ±24 mA output drive (VCC 3.0V) s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds mA s ESD performance: Human body model > 2000V Machine model 200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.

Order Number 74LCX16244G (Note 3) 74LCX16244MEA (Note 3) 74LCX16244MTD (Note 3) Package Number MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 2: Ordering code "G" indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Pin Names OEn O0­O15 NC Description Output Enable Input (Active LOW) Inputs Outputs No Connect
Inputs OE1 L Pin Assignment for FBGA H Inputs L H Inputs OE3 L (Top Thru View) H Inputs L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

The LCX16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.


 

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